IC61C256AH-12U 데이터 시트보기 (PDF) - Integrated Circuit Solution Inc

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IC61C256AH-12U

32K x 8 HIGH-SPEED CMOS STATIC RAM

Integrated Circuit Solution Inc 

IC61C256AH

WRITE CYCLE NO. 2 (CE Controlled) (1,2)

ADDRESS

OE

t WC

VALID ADDRESS

t HA

CE LOW

WE

DOUT

t SA

DATA UNDEFINED

t AW

t PWE1

t HZWE

DIN

HIGH-Z

t LZWE

t SD

t HD

DATAIN VALID

Notes:

1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if OE ≥ VIH.

8

Integrated Circuit Solution Inc.

AHSR010-0D 4/19/2002

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