HSP50214VI 데이터 시트보기 (PDF) - Intersil

부품명

상세내역

일치하는 목록

HSP50214VI

Programmable Downconverter

Intersil 

HSP50214

Summary

The greatest feature of the PDC is its ability to be reconfig-

ured to process many common standards in the communica-

tions industry. Thus, a single hardware element can receive

and process a wide variety of signals from PCS to traditional

cellular, from wireless local loop to SATCOM. The high reso-

lution frequency tuning and narrowband filtering are instru-

mental in almost all of the applications.

Multiple Chip Synchronization

Multiple PDCs are synchronized using a MASTER/SLAVE

configuration. One part is responsible for synchronizing the

front end internal circuitry using CLKIN while another part is

responsible for synchronizing the backend internal circuitry

using PROCCLK.

The PDC is synchronized with other PDCs using five control

lines: SYNCOUT, SYNCIN1, SYNCIN2, MSYNCO, and

MSYNCI. Figure 2 shows the interconnection of these five

signals for multiple chip synchronization where different

sources are used for CLKIN and PPOCCLK.

PDC A is the Master sync through MSO.

PDC B configures the CLKIN sync through SYNCIN1.

PDC A configures the PROCCLK sync through SYNCIN2.

A

B

HSP50214

(MASTER)MSO

HSP50214

MSO

MSI

(MASTER

SYNCIN2) SYNCOUT

SYNCIN2

MSI

(MASTER

SYNCOUT SYNCIN1)

SYNCIN2

SYNCIN1

SYNCIN1

ALL OTHER SYNCIN1

ALL OTHER SYNCIN2

ALL OTHER MSI

FIGURE 2. SYNCHRONIZATION CIRCUIT

SYNCOUT for PDC B should be set to be synchronous with

CLKIN (Control Word 0, bit 3 = 0. See the Microprocessor

Write Section). SYNCOUT for PDC B is tied to the SYNCIN1

of all the PDCs. The SYNCIN1 can be programmed so that

the carrier NCO and/or the 5th order CIC filter of all PDCs can

be synchronously loaded/updated using SYNCIN1. See Con-

trol Word 0, bits 19 and 20 in the Microprocessor Write Sec-

tion for details.

SYNCOUT for one of the other PDC’s besides PDC B,

should be set for PROCCLK (bit 3 = 1 in Control Word 0).

This output signal is tied to the SYNCIN2 of all PDCs. The

SYNCIN2 can be programmed so that the AGC updates its

accumulator with the contents in the master registers (Con-

trol Word 8, bit 29 in the Microprocessor Write Section).

SYNCIN2 is also used to load or reset the timing NCO using

bit 5, Control Word 11. The halfband and FIR filters can be

reset on SYNCIN2 using Control Word 7, bit 21. The

MSYNCO of one of the PDCs is then used to drive the MSI

of all the PDCs (including its own).

For application configurations where CLKIN and PROCCLK

have the same source, SYNCIN1 and SYNCIN2 can be tied

together. However, if different enabling is desired for the front

end and backend processing of the PDC’s, these signals can

still be controlled independently.

In summary, SYNCIN1 is used to update phase offset,

update center frequency, reset CIC decimation counters and

reset the carrier NCO (clear the feedback in the NCO).

SYNCIN2 is used to reset the HB filter, FIR filter,

resampler/HB state machines and the output FIFO, load a

new gain into the AGC and load a new resampler NCO cen-

ter frequency and phase offset.

Input Section

The block diagram of the input controller is provided in Fig-

ure 3. The input can support offset binary or two’s comple-

ment data and can be operated in gated or interpolated

mode (see Control Word 0 from the Microprocessor Write

Section). The gated mode takes one sample per clock when

the input enable (ENI) is asserted. The gated mode allows

the user to synchronize a low speed sampling clock to a high

speed CLKIN.

The interpolated mode allows the user to input data at a low

sample rate and to zero-stuff the data prior to filtering. This

zero stuffing effectively interpolates the input signal up to the

rate of the input clock (CLKIN). This interpolated mode

allows the part to be used at rates where the sampling fre-

quency is above the maximum input rate range of the half-

band filter section, and where the desired output bandwidth

is too wide to use a cascaded integrator comb (CIC) filter

without significantly reducing the dynamic range. See Fig-

ures 4-7 for an interpolated input example, detailing the

associated spectral results.

Interpolation Example:

The specifications for the interpolated input example are:

Input Sample Rate = 5 MSPS

PROCCLK = 28MHz

Interpolate by 8, Decimate by 10

Desired 85dB dynamic range output bandwidth = 500kHz

Input Level Detector

The Input Level Detector Section measures the average

magnitude error at the PDC input for the microprocessor by

comparing the input level against a programmable thresh-

old and then integrating the result. It is intended to provide

a gain error for use in an AGC loop with either the RF/IF or

A/D converter stages (see Figure 8). The AGC loop

includes Input Level Detector, the microprocessor and an

external gain control amplifier (or attenuator). The input

samples are rectified and added to a threshold pro-

grammed via the microprocessor interface, as shown in

Figure 9. The bit weighting of the data path through the

8

Share Link: