HSP43168(2007) 데이터 시트보기 (PDF) - Intersil
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HSP43168 Datasheet PDF : 25 Pages
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HSP43168
Coefficient sets may be switched every clock to support
polyphase filtering operations.
The coefficients are loaded into On-Board Registers using
the microprocessor interface, CIN0-9, A0-8, and WR. Each
multiplier within the FIR Cells is driven by a coefficient bank
with one of 32 coefficients. These coefficients are addressed
as shown in Table 4. The inputs A0-1 specify the Coefficient
Bank for one of the four multipliers in each FIR Cell; A2
specifies FIR Cell A or B; Bits A7-3 specify one of 32 sets in
which the coefficient is to be stored. For example, an
address of 10dH would access the coefficient for the second
multiplier in FIR B in the second coefficient set.
TABLE 4. FIR COEFFICIENT WRITE ADDRESSES
FIR CSEL (4-0)
COEFF COEFF.
.
SET
A8
A7-3
1
xxxx x
1
xxxx x
1
xxxx x
1
xxxx x
1
xxxx x
1
xxxx x
1
xxxx x
1
xxxx x
CELL
A/B
A2
0
0
0
0
1
1
1
1
MULTIPLIER
A1-0
00
01
10
11
00
01
10
11
DESTINATION
FIR BANK
A
0
A
1
A
2
A
3
B
0
B
1
B
2
B
3
FIR Cell Accumulator
The registered outputs from the multipliers in each FIR cell
feed an accumulator. The ACCEN input controls each
accumulator's running sum and the latching of data from the
accumulator into the Output Holding Registers. When
ACCEN is low, feedback from the accumulator adder is
zeroed which disables accumulation. Also, output from the
accumulator is latched into the Output Holding Registers.
When ACCEN is asserted, accumulation is enabled and the
contents of the Output Holding Registers remain unchanged.
Output MUX/Adder
The contents of each FIR Cell's Output Holding Register is
summed or multiplexed in the Mux/Adder. The operation of
the Mux/Adder is controlled by the MUX1-0 inputs as
shown in Table 5. Applications requiring 10-bit data and 20-
bit coefficients or 20-bit data and 10-bit coefficients are
made possible by configuring the MUX/Adder to scale FIR
B's output by 2-10 prior to summing with FIR A. When the
Dual FIR is configured as two independent filters, the
MUX1-0 inputs would be used to multiplex the filter outputs
of each cell. For applications in which FIR A and B are
configured as a single filter, the MUX/Adder is configured to
sum the output of each FIR cell.
NOTE: While a 20-bit coefficient filter is a single filter, the mode
select is set to 1 and MUX1-0 is set to 00.
TABLE 5. MUX1-0 BIT DEFINITIONS
MUX1-0 DECODING
MUX1-0
00
OUT0-27
FIRA + FIRB (FIR B Scaled by 2-10)
01
FIRA + FIRB
10
FIRA
11
FIRB
9
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