HN58X2402SFPIAG 데이터 시트보기 (PDF) - Renesas Electronics

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HN58X2402SFPIAG

Two-wire serial interface

Renesas Electronics 

HN58X2402SFPIAG/HN58X2404SFPIAG

Pin Function

Serial Clock (SCL)

The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into

EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz.

Serial Input/Output data (SDA)

The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is open-

drain driven structure. Use proper resistor value for your system by considering VOL, IOL and the SDA pin capacitance.

Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be

completed during the SCL low period.

Data Validity (SDA data change timing waveform)

SCL

SDA

Data

change

Data

change

Note: High-to-low and low-to-high change of SDA should be done during the SCL low period.

Rev.4.00, Jul.13.2005, page 6 of 16

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