HMP8115CN 데이터 시트보기 (PDF) - Intersil

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HMP8115CN

NTSC/PAL Video Decoder

Intersil 

HMP8115

If 16-bit YCbCr, 15-bit RGB data, or 16-bit RGB data is gen-

erated, it is output following the rising edge of CLK2 while

DVALID is asserted. Either linear or gamma-corrected RGB

data may be output. The pixel output timing is shown in Fig-

ures 12 to 15.

BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD

are output following the rising edge of CLK2. When BLANK

is asserted and VBIVALID is deasserted, the YCbCr outputs

have a value of 16 for Y and 128 for Cb and Cr; the RGB out-

puts have a value of 0.

CLK

DVALID

BLANK

P15-P8

Y0

Y1

Y2

Y3

Y4

P7-P0

Cb0

Cr0

Cb2

Cr2

Cb4

NOTES:

tDVLD

11. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate

every cycle due to the 4:2:2 subsampling.

12. BLANK is asserted per Figure 9.

FIGURE 12. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 0)

CLK

DVALID

P15-P11

[P14-P10]

R0

R1

R2

R3

R4

P10-P5

[P9-P5]

G0

G1

G2

G3

G4

P4-P0

B0

B1

B2

B3

B4

NOTE:

tDVLD

13. BLANK is asserted per Figure 9.

FIGURE 13. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 0)

13

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