HM5165165FTT-5 데이터 시트보기 (PDF) - Elpida Memory, Inc
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HM5165165FTT-5 Datasheet PDF : 36 Pages
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HM5164165F Series, HM5165165F Series
Operation Table
RAS
H
EL
L
L
OL
L
L
L L
LCAS UCAS WE
×
×
×
L
H
H
H
L
H
L
L
H
L
H
L*2
H
L
L*2
L
L
L*2
L
H
L*2
OE
×
L
L
L
×
×
×
H
I/O 0 to I/O 7
High-Z
Dout
High-Z
Dout
Din
×
Din
Din
I/O 8 to I/O 15 Operation
High-Z
Standby
High-Z
Read cycle
Dout
Dout
×
Early write cycle
Din
Din
×
Delayed write cycle
L
H
L
L*2
H
×
Din
L
L
L
L*2
H
Din
Din
L
L
H
H to L L to H Dout/Din
High-Z
Read-modify-write cycle
L
H
L
H to L L to H High-Z
Dout/Din
P L
L
L
H to L L to H Dout/Din
L
H
H
×
×
High-Z
H to L H
L
H
×
High-Z
Dout/Din
High-Z
High-Z
RAS-only refresh cycle
CAS-before-RAS refresh cycle or
H to L L
H
H
×
High-Z
High-Z
Self refresh cycle (L-version)
r HtoL L
L
H
×
High-Z
High-Z
o L
L
L
H
H
High-Z
High-Z
Read cycle (Output disabled)
Notes: 1. H: VIH (inactive) L: VIL (active) ×: VIH or VIL
2. tWCS ≥ 0 ns: Early write cycle
tWCS < 0 ns: Delayed write cycle
d 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliestof UCAS
and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write
operation and output High-Z control are done independently by each UCAS, LCAS.
uct ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected.
Data Sheet E0099H10
7
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