HM5117805LTS-7 데이터 시트보기 (PDF) - Elpida Memory, Inc

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HM5117805LTS-7

16 M EDO DRAM (2-Mword × 8-bit) 2 k Refresh

Elpida Memory, Inc 

HM5117805 Series

Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)

HM5117805

-5

-6

Parameter

Symbol Min Max Min

Random read or write cycle time tRC

RAS precharge time

t RP

CAS precharge time

t CP

RAS pulse width

t RAS

CAS pulse width

t CAS

Row address setup time

t ASR

Row address hold time

t RAH

Column address setup time

t ASC

Column address hold time

t CAH

RAS to CAS delay time

t RCD

RAS to column address delay time tRAD

RAS hold time

t RSH

CAS hold time

t CSH

CAS to RAS precharge time

t CRP

OE to Din delay time

t OED

OE delay time from Din

t DZO

CAS delay time from Din

t DZC

Transition time (rise and fall)

tT

84 — 104

30 — 40

7 — 10

50 10000 60

7 10000 10

0—0

7 — 10

0—0

7 — 10

11 37 14

9 25 12

10 — 13

35 — 40

5—5

13 — 15

0—0

0—0

2 50 2

-7

Max Min

— 124

— 50

— 13

10000 70

10000 13

—0

— 10

—0

— 13

45 14

30 12

— 13

— 45

—5

— 18

—0

—0

50 2

Max Unit

— ns

— ns

— ns

10000 ns

10000 ns

— ns

— ns

— ns

— ns

52 ns

35 ns

— ns

— ns

— ns

— ns

— ns

— ns

50 ns

Notes

3

4

5

6

6

7

Data Sheet E0156H10

8

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