HI1-0506-2(2005) 데이터 시트보기 (PDF) - Intersil

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HI1-0506-2
(Rev.:2005)

Single 16 and 8/Differential 8-Channel and 4-Channel CMOS Analog Multiplexers

Intersil 

HI-506, HI-507, HI-508, HI-509

Plastic Leaded Chip Carrier Packages (PLCC)

0.042 (1.07)

0.048 (1.22)

PIN (1) IDENTIFIER

CL

0.042 (1.07)

0.056 (1.42)

0.050 (1.27) TP

0.004 (0.10) C

0.025 (0.64)

0.045 (1.14)

R

CL

E1 E

D2/E2

D2/E2

VIEW “A”

0.020 (0.51) MAX

3 PLCS

D1

D

0.026 (0.66)

0.032 (0.81)

0.020 (0.51)

A1

MIN

A

-C-

SEATING

PLANE

0.013 (0.33)

0.021 (0.53)

N28.45 (JEDEC MS-018AB ISSUE A)

28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

INCHES

MILLIMETERS

SYMBOL MIN

MAX

MIN

MAX NOTES

A

0.165 0.180 4.20

4.57

-

A1

0.090 0.120 2.29

3.04

-

D

0.485 0.495 12.32 12.57

-

D1

0.450 0.456 11.43 11.58

3

D2

0.191 0.219 4.86

5.56

4, 5

E

0.485 0.495 12.32 12.57

-

E1

0.450 0.456 11.43 11.58

3

E2

0.191 0.219 4.86

5.56

4, 5

N

28

28

6

Rev. 2 11/97

0.045 (1.14)

MIN

0.025 (0.64)

MIN

VIEW “A” TYP.

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimensions are

not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Allowable

mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1

and E1 include mold mismatch and are measured at the extreme

material condition at the body parting line.

4. To be measured at seating plane -C- contact point.

5. Centerline to be determined where center leads exit plastic body.

6. “N” is the number of terminal positions.

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reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

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23

FN3142.7

July 21, 2005

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