HI-8591 데이터 시트보기 (PDF) - Holt Integrated Circuits
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HI-8591 Datasheet PDF : 7 Pages
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HI-8591
FUNCTIONAL DESCRIPTION
RECEIVER
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each require 140KW of resis-
tance between the ARINC bus and comparator. This resis-
tance is completely on-chip for the HI-8591. In contrast,
the HI-8591-40 has 100 KW on-chip and requires an exter-
nal 40KW, ¼ watt resistor on each of the ARINC 429 input
pins. The HI-8591-40 device is typically chosen for appli-
cations where lightning protection is a requirement.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differ-
ential signal is compared to levels derived from a divider
between V.C. and Ground. The nominal settings corre-
spond to a One/Zero amplitude of 6.0V and a Null ampli-
tude of 3.3V.
The status of the ARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. If TESTA and TESTB are both One, the HI-
8591 outputs are pulled low. This allows the digital out-
puts of a transmitter to be connected to the test inputs
through control logic for system self-test purposes.
RINA
RINB
ESD
PROTECTION
AND
TRANSLATION
ONE
NULL
ZERO
NULL
SQ
LATCH
R
TEST
TESTA
TESTB
SQ
LATCH
R
TEST
TESTA
TESTB
FIGURE 1 - RECEIVER BLOCK DIAGRAM
ROUTA
ROUTB
HARDWIRE
OR
{
DRIVE FROM LOGIC
APPLICATION INFORMATION
Figure 2 shows a possible application of the
HI-8591 interfacing an ARINC 429 bus input
to a 3.3V ASIC or FPGA. In this example a
HI-8586 ARINC 429 line driver is used to
take 3.3V logic outputs and generate the nec-
essary 10V differential signal for driving an
ARINC 429 bus.
ARINC
Channel
ARINC
Channel
3.3V
1
2
VCC
TESTA
ROUTA
6
8
TESTB
7
ROUTB
4 HI-8591
RINA
3
RINB GND
5
15V
1
8
SLP1.5 V+
6 TXAOUT
3
TX1IN
7
HI-8586
TXBOUT
TX0IN
2
GND V-
45
-15V
FIGURE 2 - APPLICATION DIAGRAM
RXD1
RXD0
FPGA
TXD1
TXD0
HOLT INTEGRATED CIRCUITS
2
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