NXP Semiconductors
HEF4067B
16-channel analog multiplexer/demultiplexer
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Test data is given in Table 10.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator
CL = load capacitance including jig and probe capacitance
RL = load resistor
S1 = test selection switch
Fig 12. Test circuit for measuring switching times
Table 10. Test data
Input
Yn, Z
An and E tr, tf
VDD or VSS VDD or VSS 20 ns
VM
0.5VDD
Load
CL
50 pF
RL
10 k
S1 position
tPHL[1]
tPLH
VDD or VSS VSS
tPZH, tPHZ tPZL, tPLZ other
VSS
VDD
VSS
[1] For Yn to Z or Z to Yn propagation delays use VSS. For An or to Yn or Z propagation delays use VDD.
HEF4067B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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