GS820322T-138 데이터 시트보기 (PDF) - Unspecified

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GS820322T-138

64K x 32 2M Synchronous Burst SRAM

Unspecified 

TQFP Pin Description

Pin Location

Symbol

37, 36

35, 34, 33, 32, 100, 99, 82, 81, 44, 45,

46, 47, 48, 49

A0, A1

A2–A15

52, 53, 56, 57, 58, 59, 62, 63

68, 69, 72, 73, 74, 75, 78, 79

2, 3, 6, 7, 8, 9, 12, 13

18, 19, 22, 23, 24, 25, 28, 29

16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30

DQA1–DQA8

DQB1–DQB8

DQC1–DQC8

DQD1–DQD8

NC

87

BW

93, 94

95, 96

89

BA, BB

BC, BD

CK

88

GW

98, 92

97

86

E1, E3

E2

G

83

ADV

84, 85

ADSP, ADSC

64

ZZ

14

FT

31

LBO

15, 41, 65, 91

5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90

4, 11, 20, 27, 54, 61, 70, 77

VDD

VSS

VDDQ

Type

I

I

I/O

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

Preliminary

GS82032T/Q-150/138/133/117/100/66

Description

Address field LSBs and Address Counter preset Inputs

Address Inputs

Data Input and Output pins

No Connect

Byte Write—Writes all enabled bytes; active low

Byte Write Enable for DQA, DQB Data I/Os; active low

Byte Write Enable for DQC, DQD Data I/Os; active low

Clock Input Signal; active high

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Core power supply

I/O and Core Ground

Output driver power supply

Rev: 1.04 2/2001

3/23

© 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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