GS1504-CTD(2000) 데이터 시트보기 (PDF) - Gennum -> Semtech
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GS1504-CTD Datasheet PDF : 12 Pages
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APPLICATION INFORMATION
PCB LAYOUT
Special attention must be paid to component layout when
designing serial digital interfaces for HDTV. Figures 23
through 27 show the artwork for a four layer printed circuit
evaluation board for the GS1504. The schematic is shown in
Figure 22. An FR-4 dielectric can be used, however,
controlled impedance transmission lines are required for
PCB traces longer than approximately 1cm. Note the
following PCB artwork features used to optimize
performance:
• PCB trace width for HD rate signals is closely matched
to SMT component width to minimize reflections due to
change in trace impedance.
• The PCB ground plane is removed under the GS1504
input components to minimize parasitic capacitance.
• The PCB ground plane is removed under the GS1504
output components to minimize parasitic capacitance.
• High speed traces are curved to minimize impedance
changes.
A picture of the GS1504 PCB assembly is shown in Figure
28.
GS1504 EVALUATION BOARD
VCC
TP1
J5
VCC
R1
75
10n
L4
C6
J1
10nH
R4
47p
75
C7
C8
47p
37
R2
10n
C5
1 CLI CD/MUTE 16
2 VCC
3 VEE
4 SDI
VCC 15
VEE 14
SDO 13
5 SDI
SDO 12
6 VEE
7 MCLADJ
VEE 11
NC 10
8 NC
NC 9
2k
J4
R5
VCC
C3
10n
10n
C4
VCC
4.7µ
J2
+ C1
+ C2
4.7µ
J3
C1, C2 must be tantalum
capacitors.
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
10k
R3
C10
C9
C11
1µ
100n 1n
15k
R6
Fig. 22 GS1504 Application Schematic
9
522 - 05 - 02
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