AD974BRS 데이터 시트보기 (PDF) - Analog Devices
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AD974BRS Datasheet PDF : 20 Pages
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AD974
Parameter
DIGITAL OUTPUTS
Data Format
Data Coding
VOL
VOH
Output Capacitance
Leakage Current
POWER SUPPLIES
Specified Performance
VDIG
VANA
IDIG
IANA
Power Dissipation
PWRD LOW
PWRD HIGH
Conditions
ISINK = 1.6 mA
ISOURCE = 500 µA
High-Z State
High-Z State
VOUT = 0 V to VDIG
A Grade
Min Typ Max
B Grade
Min Typ Max
Serial 16 Bits
Straight Binary
+0.4
+0.4
+4
+4
15
15
±5
±5
Units
V
V
pF
µA
+4.75 +5
+4.75 +5
4.5
14
50
+5.25
+5.25
120
+4.75 +5 +5.25
V
+4.75 +5 +5.25
V
4.5
mA
14
mA
120
mW
50
µW
TEMPERATURE RANGE
Specified Performance
TMIN to TMAX
–40
+85
–40
+85
°C
NOTES
1LSB means Least Significant Bit. With a ±10 V input, one LSB is 305 µV.
2Typical rms noise at worst case transitions and temperatures.
3Full-Scale Error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scale transition voltage, and includes the effect
of offset error. For bipolar input, the Full-Scale Error is the worst case of either the –Full-Scale or +Full-Scale code transition voltage errors. For unipolar input
ranges, Full-Scale Error is with respect to the +Full-Scale code transition voltage.
4External 2.5 V reference connected to REF.
5All specifications in dB are referred to a full-scale ±10 V input.
6Full-Power Bandwidth is defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB, or 10 bits of accuracy.
7Recovers to specified performance after a 2 × FS input overvoltage.
Specifications subject to change without notice.
TIMING SPECIFICATIONS (fS = 200 kHz, VDIG = VANA = +5 V, –40؇C to +85؇C)
Parameter
Symbol
Min
Typ
Max
Units
Convert Pulsewidth
R/C, CS to BUSY Delay
BUSY LOW Time
BUSY Delay after End of Conversion
Aperture Delay
Conversion Time
Acquisition Time
Throughput Time
R/C Low to DATACLK Delay
DATACLK Period
DATA Valid Setup Time
DATA Valid Hold Time
EXT. DATACLK Period
EXT. DATACLK HIGH
EXT. DATACLK LOW
R/C, CS to EXT. DATACLK Setup Time
R/C to CS Setup Time
EXT. DATACLK to SYNC Delay
EXT. DATACLK to DATA Valid Delay
CS to EXT. DATACLK Rising Edge Delay
Previous DATA Valid after CS, R/C Low
BUSY to EXT. DATACLK Setup Time
Final EXT. DATACLK to BUSY Rising Edge
A0, A1 to WR1, WR2 Setup Time
A0, A1 to WR1, WR2 Hold Time
WR1, WR2 Pulsewidth
Specifications subject to change without notic e.
t1
t2
t3
t4
t5
t6
t7
t6 + t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
50
ns
100
ns
4.0
µs
50
ns
40
ns
3.8
4.0
µs
1.0
µs
5
µs
220
ns
220
ns
50
ns
20
ns
66
ns
20
ns
30
ns
20
t12 + 5
ns
10
ns
15
66
ns
25
66
ns
10
ns
3.5
µs
5
ns
1.7
µs
10
ns
10
ns
50
ns
REV. A
–3–
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