HEC40195BDB 데이터 시트보기 (PDF) - Philips Electronics

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HEC40195BDB

4-bit universal shift register

Philips Electronics 

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Dynamic power

dissipation per

package (P)

VDD

V

TYPICAL FORMULA FOR P (µW)

5

1900 fi + ∑ (foCL) × VDD2

10

8300 fi + ∑ (foCL) × VDD2

15

22 800 fi + ∑ (foCL) × VDD2

where

fi = input freq. (MHz)

fo = output freq. (MHz)

CL = load capacitance (pF)

∑ (foCL) = sum of outputs

VDD = supply voltage (V)

Fig.4 Waveforms showing set-up times, hold times for J, K and Pn inputs; minimum MR pulse width, MR to output delays and MR to CP

recovery time; minimum CP pulse width and CP to output delays. Set-up and hold times are shown as positive values but may be specified

as negative values.

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