Micrel
TIMING DIAGRAMS (CONTINUED)
SY10E446
SY100E446
CLK
RESET
D0
D1
D2
D3
D4(D0B)
D5(D1B)
D6(D2B)
D7(D3B)
SOUT
D0–1
D0–2
D1–1
D1–2
D2–1
D3–1
D2–2
D3–2
D4–1
D4–2
D5–1
D5–2
D6–1
D7–1
D6–2
D7–2
D0–1 D1–1 D2–1 D3–1 D4–1 D5–1 D6–1 D7–1 D0–2 D1–2
CL/4
CL/8
Timing Diagram B. 8:1 Parallel-to-Serial Conversion
5