HTG13J0 데이터 시트보기 (PDF) - Holtek Semiconductor

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HTG13J0

4-Bit Microcontroller

Holtek Semiconductor 

The Timer is presettable and readable with

software instructions. "TIMER XXH", "MOV

TMRL,A" and "MOV TMRH,A" preload TIMER

value. "MOV A,TMRL" and "MOV A,TMRH"

read the contents of the TIMER to ACC.

The Timer is stopped by a hardware reset or

"TIMER OFF" instruction and started by a

TIMER ON instruction.

Once the Timer is started, it will increment to its

maximum count (FFH) and overflow to zero

(00H) and will not stop until there is a TIMER

OFF instruction or reset. When an overflow oc-

curs, it will set the Timer Flag (TF) simulta-

neously. If interrupt is enabled, the Timer circuit

supports TF for internal interrupt. The state of

the TF is also testable with conditional instruc-

tion JTMR.

The Timer flag is cleared after the interrupt or

JTMR instruction is executed.

The frequency of internal frequency source can

be selected by mask option.

=

m

2n

Where n=0, 1, 2......13 except 6, by mask option

(the sixth stage is reserved for internal use).

Interrupt

The HTG13J0 provide both internal and exter-

nal interrupt modes. The DI and EI instruc-

tions are used to disable and enable the

interrupts. During halt mode, if the PP or PS

input pin is triggered on a high to low transition

in the enable interrupt mode and the program

is not within a CALL subroutine the external

interrupt is activated. This causes a subroutine

call to location 8 and resets the interrupt latch.

Likewise when the timer flag is set in the en-

able interrupt mode and the program is not

within a CALL subroutine, the internal inter-

rupt is activated. This causes a subroutine call

to location 4 and resets the timer flag.

When running under a CALL subroutine or DI,

the interrupt acknowledge is on hold until the

RET or EI instruction is invoked. The CALL in-

struction should not be used within an inter-

rupt routine as unpredictable result may occur.

HT13J0

If within a CALL subroutine, an interrupt oc-

curs, the interrupt will be serviced after leaving

the CALL subroutine.

The interrupts are disabled by a hardware re-

set or a DI instruction. They remain disabled

until the EI instruction is executed.

Each input port pin can be programmed by

mask option to have an external interrupt func-

tion in the HALT mode.

Initial reset

The HTG13J0 provide a RES pin for system ini-

tialization. Since the RES pin has internal pull

high resistor, only an external 0.1m~1m capacitor

is needed. If the reset pulse is generated exter-

nally, it must be held low for at least 5 ms.

When RES is active, the internal block will be

initialized as follows:

PA3 and PC 1000H

TIMER

Stop

Timer flag

Reset (low)

SOUND

Sound off and One sing mode

Output Port A high (or floating state)

Interrupt

Disabled

BZ and BZ

output

High level

Halt

This is a special feature of HTG13J0. It will stop

the chip s normal operation and reduce power

consumption. When the instruction HALT is

executed, then either of the following will occur:

· The system clock will be stopped

· The contents of the on-chip RAM and regis-

ters remain unchanged

· LCD segments and commons keep VDD volt-

age (i.e. LCD becomes blank)

The system can leave the HALT mode by ways

of initial reset or external interrupt and

wake-up from the following entry of the pro-

gram counter value.

11

May 19, 1999

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