MC14076BCL 데이터 시트보기 (PDF) - Motorola => Freescale
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MC14076BCL Datasheet PDF : 6 Pages
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INPUT RISE AND FALL 20 ns
INPUT
D INFORMATION
tsu
90%
50%
10%
th
tsu
VDD
th
VSS
20 ns
50%
90%
VDD
tWH
tWL
10% VSS
tPLH
Q OUTPUT
fcl
90%
10%
tTLH
tPHL VOH
50%
tTHL
VOL
RESET = 0
DATA DISABLE A AND B = 0
OUTPUT DISABLE A AND B = 0
Figure 1. Timing Diagram
EQUIVALENT
FUNCTIONAL BLOCK DIAGRAM
OUTPUT DISABLE A 1
OUTPUT DISABLE B 2
D0 14
DATA DISABLE A 9
DATA DISABLE B 10
DQ
C RQ
D1 13
CLOCK 7
D2 12
DQ
C RQ
DQ
C RQ
OUTPUT
DISABLE
A OR B
ANY Q
OUTPUT
ANY Q
OUTPUT
20 ns
90%
50%
50%
tPLZ
10%
tPHZ
90%
20 ns
10%
tPZL
90%
tPZH
10%
OUTPUTS
CONNECTED
OUTPUTS
DISCONNECTED
VDD
VSS
VOH
≈ 2.5 V @ VDD = 5 V,
10 V, AND 15 V
≈ 2 V @ VDD = 5 V
≈ 6 V @ VDD = 10 V
≈ 10 V @ VDD = 15 V
VOL
OUTPUTS
CONNECTED
OTHER
INPUTS
OUTPUT
DISABLE
A OR B
MC14076B
ANY Q
OUTPUT
RL = 1 kΩ
CL
VDD FOR tPLZ AND tPZL
VSS FOR tPHZ AND tPZH
Figure 2. Three–State Propagation Delay
Waveshape and Circuit
3 Q0
4 Q1
PIN ASSIGNMENT
{ OUTPUT A 1
DISABLE B 2
Q0 3
Q1 4
Q2 5
Q3 6
C7
VSS 8
16 VDD
15 R
14 D0
13 D1
12 D2
11 D3
} 10 B DATA
9 A DISABLE
5 Q2
D3 11
RESET 15
DQ
C RQ
6 Q3
MC14076B
4
MOTOROLA CMOS LOGIC DATA
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