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EPF10K50

Embedded Programmable Logic Device Family

Altera Corporation 

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Larger blocks of RAM are created by combining multiple EABs. For

example, two 256 × 8 RAM blocks can be combined to form a

256 × 16 RAM block; two 512 × 4 blocks of RAM can be combined to form

a 512 × 8 RAM block. See Figure 3.

Figure 3. Examples of Combining EABs

256 × 16

256 × 8

512 × 8

512 × 4

256 × 8

512 × 4

If necessary, all EABs in a device can be cascaded to form a single RAM

block. EABs can be cascaded to form RAM blocks of up to 2,048 words

without impacting timing. Altera’s software automatically combines

EABs to meet a designer’s RAM specifications.

EABs provide flexible options for driving and controlling clock signals.

Different clocks can be used for the EAB inputs and outputs. Registers can

be independently inserted on the data input, EAB output, or the address

and WE inputs. The global signals and the EAB local interconnect can drive

the WE signal. The global signals, dedicated clock pins, and EAB local

interconnect can drive the EAB clock signals. Because the LEs drive the

EAB local interconnect, the LEs can control the WE signal or the EAB clock

signals.

Each EAB is fed by a row interconnect and can drive out to row and

column interconnects. Each EAB output can drive up to two row channels

and up to two column channels; the unused row channel can be driven by

other LEs. This feature increases the routing resources available for EAB

outputs. See Figure 4.

Altera Corporation

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