AN-6920MR 데이터 시트보기 (PDF) - Fairchild Semiconductor

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AN-6920MR

Integrated Critical-Mode PFC / Quasi-Resonant Current-Mode PWM Controller FAN6920

Fairchild Semiconductor 

AN-6920

[STEP-A3] Design VIN Sense Circuit

FAN6920 senses the line voltage using the averaging circuit

shown in Figure 12, where the VIN pin is connected to the

AC line through a voltage divider and low-pass filter

capacitor. When VIN drops below 1V, the COMP pin is

clamped at 1.6V to limit the energy delivered to output.

VO.PFC decreases with the INV pin voltage. When the INV

pin voltage drops below 1V, brownout protection is

triggered, stopping gate drive signals of PFC and DC/DC.

This protection is reset when VDD drops below the turn-off

threshold (UVLO threshold). When VDD rises to the turn-on

voltage after dropping below the turn-off threshold,

FAN6920 resumes normal operation (if VIN is above 1.2V).

The brownout protection level can be determined as:

VLINE.BO

=

π

22

⋅

RVIN1 + RVIN 2

RVIN 2

(12)

The minimum line voltage for PFC startup is given as:

VLINE.STR = 1.2 ⋅VLINE.BO

(13)

APPLICATION NOTE

(Design Example) Choosing the margin factor as 35%,

the sensing resistor is selected as:

0.82

0.82

RCS1 = I L.PK (1+ KMARGIN ) = 3.14(1+ 0.35) = 0.19Ω

[STEP-A6] Design Compensation Network

The feedback loop bandwidth must be lower than 20Hz for

the PFC application. If the bandwidth is higher than 20Hz,

the control loop may try to reduce the 120Hz ripple of the

output voltage and the line current is distorted, decreasing

power factor. A capacitor is connected between COMP and

GND to attenuate the line frequency ripple voltage by 40dB.

If a capacitor is connected between the output of the error

amplifier and the GND, the error amplifier works as an

integrator and the error amplifier compensation capacitor

can be calculated by:

CCOMP

>

100⋅ gM

2π ⋅ 2 fLINE

2.5

⋅

VO.PFC.H

(15)

To improve the power factor, CCOMP must be higher than the

calculated value. However, if the value is too high, the

output voltage control loop may become slow.

(Design Example)

CCOMP

>

100 ⋅ gM

2π ⋅ 2 fLINE

2.5

⋅

VO.PFC.H

100 ⋅125×10−6 2.5

=

⋅ = 103nF

2π ⋅ 2 ⋅ 60 400

470nF is selected for better power factor.

Figure 12. VIN Sensing Internal Block

(Design Example) Setting the brownout protection trip point

as 69VAC:

RVIN1 + RVIN 2

RVIN 2

22

= VLINE.BO ⋅ π

= 62

Determining RVIN2 as 154kΩ, RVIN1 is determined as 9.4MΩ.

The line voltage to startup the PFC is obtained as:

VLINE.STR = 1.2 ⋅VLINE.BO = 83VAC

[STEP-A4] Current Sensing Resistor for PFC

FAN6920 has pulse-by-pulse current limit function. It is

typical to set the pulse-by-current limit level at 20~30%

higher than the maximum inductor current:

RCS1

=

0.82

IL.PK (1 + KMARGIN )

(14)

where KMARGIN is the margin factor and 0.82V is the pulse-

by-pulse current limit threshold.

Part B. DC/DC Section

[STEP-B1] Determine the Secondary-Side Rectifier

Voltage (VDnom)

Figure 13 shows the typical operation waveforms of a dual-

switch quasi-resonant flyback converter. When the

MOSFET is turned off, the input voltage (PFC output

voltage), together with the output voltage reflected to the

primary (VRO), is imposed on the MOSFET. When the

MOSFET is turned on, the sum of input voltage reflected to

the secondary side and the output voltage is applied across

the secondary-side rectifier. Thus, the maximum nominal

voltage across the MOSFET (Vdsnom) and diode are given as:

V nom

DS

=

VO.PFC

+

n(VO

2

+ VF )

=

VO.PFC + VRO

2

(16)

where:

n = NP = VRO

NS VO + VF

V nom

D

= VO

+

VO.PFC

n

(17)

© 2010 Fairchild Semiconductor Corporation

Rev. 1.0.0 • March 10, 2011

7

www.fairchildsemi.com

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