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FAN5109B

Dual Bootstrapped 12V MOSFET Driver

Fairchild Semiconductor 

Electrical Characteristics

VCC and VLDRV = 12V and TA = 25°C using the circuit in Figure 4, unless otherwise noted, each side. The “•” denotes

specifications that apply over the full operating temperature range.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Input Supply

VCC

VCC Voltage Range

ICC

VCC Current

OD = 0V

• 6.4

•

12.0 13.5

V

2.5

4.0

mA

OD Input

VIH (OD) Input High Voltage

VIL (OD)

Input Low Voltage

VHYS(OD) Input Hysteresis

IOD

Input Current

tpdl(OD)

tpdh(OD)

Propagation Delay(4)

PWM Input

VIH(PWM) Input High Voltage

VIL(PWM) Input Low Voltage

VHYS(PWM)

IIL(PWM)

Input Hysteresis

Input Current

High-Side Driver

RHUP

Output Resistance, Sourcing

ISOURCE(LDRV) Source Current(4)

RHDN

ISINK(HDRV)

Output Resistance, Sinking

Sink Current(4)

tR(HDRV)

tF(HDRV)

Transition Times(4,6)

tpdh(HDRV)

tpdl(HDRV)

Propagation Delay(4,5)

Low-Side Driver

RLUP

Output Resistance, Sourcing

ISOURCE(LDRV) Source Current(4)

RLDN

ISINK(LDRV)

BGth

Output Resistance, Sinking

Sink Current(4)

Bottom Gate Threshold(4)

tR(LDRV)

tF(LDRV)

Transition Times(4,6)

tpdh(LDRV)

tpdl(LDRV)

Propagation Delay(4,5)

tpdh(LDF)

•

•

•

OD = 3.0V

•

See Figure 5

•

•

•

VBOOT – VSW = 12V

VDS = -10V

VBOOT – VSW = 12V

VDS = 10V

See Figure 4

See Figure 6

VDS = -10V

VDS = 10V

See Figure 4

See Figure 6

See Adaptive Gate Drive

Circuit Description

2.0

250

–300

2.0

200

-1

1.0

V

0.8

V

550

mV

+300 nA

25

40

ns

15

30

ns

V

0.8

V

550

mV

+1

µA

2.5

3.3

Ω

2.0

A

1.1

1.5

Ω

2.5

A

25

40

ns

15

25

40

55

ns

25

40

2.0

2.6

Ω

2.5

A

0.9

1.2

Ω

2.5

A

1.2

1.6

V

20

30

ns

15

25

ns

20

30

ns

15

25

ns

140

ns

Notes:

3. Limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality control.

4. Specifications guaranteed by design and characterization (not production tested).

5. For propagation delays, tpdh refers to low-to-high signal transition. tpdl refers to high-to-low signal transition.

6. Transition times are defined for 10% and 90% of DC values.

© 2006 Fairchild Semiconductor Corporation

FAN5109B Rev. 1.0.0

5 of 14

www.fairchildsemi.com

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