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EN25D16

16 Megabit Serial Flash Memory with 4Kbyte Uniform Sector and Dual Output

Eon Silicon Solution Inc. 

EN25D16

Write Disable (WRDI) (04h)

The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status

Register to a 0 or exit from OTP mode to normal mode. The Write Disable instruction is entered by

driving Chip Select (CS#) low, shifting the instruction code “04h” into the DI pin and then driving Chip

Select (CS#) high. Note that the WEL bit is automatically reset after Power-up and upon completion

of the Write Status Register, Page Program, Sector Erase, Block Erase (BE) and Chip Erase

instructions.

Figure 6. Write Disable Instruction Sequence Diagram

Read Status Register (RDSR) (05h)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register

may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress.

When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit

before sending a new instruction to the device. It is also possible to read the Status Register continuously,

as shown in Figure 7.

Figure 7. Read Status Register Instruction Sequence Diagram

This Data Sheet may be revised by subsequent versions 12 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

Rev. B, Issue Date: 2008/06/23

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