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EM92600/1A
DUAL PLL FOR 46/49 MHZ CORDLESS PHONE
TIMING DIAGRAM
Data
Clock
Enable
D3
tw
1 st
CLK
PDT
LD
APPLICATION CIRCUIT
D2
tsu th
2 nd
CLK
D1
3 rd
CLK
EM92601A Timing
1.6µS
D0
4 th
CLK tw
tsu
1 st
CLK
trec
Previous
Data Latched
6.4±0.4mS
Unlock Timing
0.455MHz
2ND IF
2ND
MIX
1ST IF
1ST
MIX
BPF
RX
VCO
LPF
LPF
TX
VCO
BPF
16 15 14 13 12 11 10 9
10.240
MHz
12 34 56 78
* This specification are subject to be changed without notice.
4.23.1995 5