EL4501 데이터 시트보기 (PDF) - Intersil

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EL4501

Video Front End

Intersil 

Block Diagram

INPUT

VIDEO

VIDEO IN

0.1µF

SYNC IN

0.1µF

FSEL

SYNC AMP

LOS

RFREQ

EL4501

VS

VSD

DS REF

FILTER

+

-

+

-

+

-

TRACK/

HOLD

+

-

1.3V

SYNC

SEPARATOR

DS MODE

DS OUT

DS ENABLE

VIDEO OUT

VFB

RF

CHOLD

RG

REF IN

REF OUT

CREF

BACK PORCH

COMPOSITE

HORIZONTAL

VERTICAL

ODD/EVEN

GND

SLICE

MODE

GNDD

Applications Information

Product Description

The EL4501 is a video front-end sub-system comprised of a

video amplifier with DC-restore, an adjustable threshold data

slicer, and an advanced sync separator. The prime function

of the system is to DC-stabilize and buffer AC-coupled

analog video signals and to extract timing reference signals

embedded in the video signal. An adjustable threshold data

slicer incorporated into the EL4501 may be used to extract

data embedded within the active video or VBI regions of a

video signal.

Theory of Operation

DC-RESTORE LOOP

When video signals are distributed, it is common to employ

capacitive coupling to prevent DC current flow due to

differences in local grounds or signal reference levels.

However, the coupling capacitor causes the DC level of the

signal post capacitor to be dependent on the video

(luminance) content of the waveform. A DC-restore loop is

used to correct this behavior by moving a portion of the

video waveform to a DC reference level in response to a

control signal. When the loop is operating, DC drift

15

accumulates over a single line only, before it is corrected.

The peak value of drift is limited by the rate of the control

signal (typically video line rate) and the AC coupling time

constant.

The restore loop is comprised of a 100MHz forward video

amplifier, combined with a nulling amplifier and sample and

hold circuit. For maximum flexibility the hold capacitor is

placed off-chip, allowing the loop response rate to be tailored

for specific applications and minimizing hold-step problems.

The loop provides a restore current peak of ±20µA at room

temperature. Figure 36 shows the amplifier and S/H

connection. During normal operation the internally generated

DC-restore control signal is timed to the back porch of the

video waveform. Figure 37 shows an NTSC video signal,

along with the EL4501 BACK PORCH output. In operation,

BACK PORCH activates the S/H switch, completing the

nulling feedback loop and driving the video amplifier output

towards the reference voltage. At the end of BACK PORCH,

the external capacitor holds the correction voltage for the

remainder of the video line. In the absence of a valid input

signal, the chip generates a repetitive, arbitrary restore

control signal at the line rate set by the external resistor

RFREQ. Although uncorrelated to the input, the pulse

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