EL4501(2004) 데이터 시트보기 (PDF) - Intersil

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EL4501
(Rev.:2004)

Video Front End

Intersil 

EL4501

Low jitter, temperature-stable timing signals are generated

using a master time-base, embedded within the system. Line

rate is adjustable from 10kHz to 135kHz using a single

external resistor (RFREQ). An integrated, pin-selectable

digital filter tracks line rate and rejects high frequency noise

and video artifacts, such as color burst. In addition to the

digital filter, a window-based, time qualification scheme is

employed to improve recovered signal quality. During loss of

signal, all outputs are blanked to prevent output chatter

caused by input noise.

Composite Sync Output

The composite sync output is a reproduction of the signal

waveform below the composite video black level, with the

video completely removed. The composite video signal is

AC-coupled to SYNC IN (pin 9). The video signal passes

through a comparator whose threshold is controlled by the

SLICE MODE pin. The output of the comparator is buffered

to the COMPOSITE output (pin 11) as a CMOS logic signal.

Horizontal Sync Output

The horizontal circuit triggers on the falling edge of the sync

tip of the input composite video signal and produces a

horizontal output with pulse widths about 12 times the

internal oscillator clock. For NTSC video input, the pulse

width of the horizontal sync is 1.5µs, with the digital filter

selected. The half line pulses present in the input signal

during vertical blanking are removed with an internal

2H-eliminator circuit.

Vertical Sync Output

A low-going vertical sync pulse is generated during the start

of the vertical cycle of the incoming composite video signal.

The vertical output pulse is started on the first serration

pulse in the vertical interval and is ended on the second

rising edge during the vertical serration phase. In the

absence of vertical serration pulses, a vertical sync pulse will

be forced out after the vertical sync default delay time,

approximately 31µs after the last falling edge of the vertical

pre-equalizing pulse for RFREQ = 130kΩ.

Back Porch Output

In a composite video signal, the chroma burst is located on

the back porch of the horizontal blanking period and is also

the black level reference for the subsequent video scan line.

The back porch is triggered from the rising edge of the sync

tip. The pulse width of the back porch is about 29 times the

internal oscillator clock cycle. For the NTSC video input, the

pulse width of the back porch is about 3.5µs. In EL4501, the

back porch pulse controls the sample and hold switch of the

DC-restored loop.

Odd and Even Output

For a composite video signal that is interlaced, there is an

odd field that includes all the odd lines, and an even field that

consists of the even lines. The odd and even circuit tracks

the relationship of the horizontal pulses to the leading edge

of the vertical output and will switch on every field at the start

of vertical sync pulse interval. ODD/EVEN, pin 14 is high

during the odd field and low during the even field.

Sync Amplitude Output

The output voltage at the SYNC AMP output (pin 17) is

about 2 times the sync tip voltage. This signal can be used

for AGC applications. When there is no sync signal at the

input, the SYNC AMP output is 0V.

Loss of Sync Output

Loss of video signal can be detected by monitoring the LOS

output at pin 10. LOS goes low indicating the EL4501 has

locked to the right line rate. LOS goes high indicating the

EL4501 is out of lock. When there is loss of sync, all the

sync outputs go high, except ODD/EVEN.

Digital Filter Operation

The EL4501 contains a user-selectable digital filter which

tracks the line rate and rejects high frequency noise and

video artifacts, such as color burst. Basically, the digital filter

delays all signals and filters out the pulses which are shorter

than the filters delay time. The digital filter greatly reduces

the jitters in the outputs. With the digital filter on, the jitter at

the composite sync output is only 2ns. Figure 39 shows the

jitter at the output when the digital filter is selected. However,

the output waveforms will be delayed from 150ns to 300ns

due to this filter. Refer to the performance curves for details.

Applying logic high to the FSEL pin, the digital filter is

enabled. Applying a logic low to the FSEL pin, the digital

filter is disabled.

CH2=2V/DIV

M=2ns

FIGURE 39. JITTER AT THE OUTPUTS WITH FSEL=1

RFREQ

An external RFREQ resistor, connected from pin 7 to ground,

produces a reference current that is used internally as the

timing reference for all the sync output delay time and output

pulse widths. Decreasing the value of RFREQ increases the

reference current and frequency of the internal oscillator,

which in turn decreases the reference time and pulse width.

A higher frequency video input requires a lower RFREQ

value. The Line Rates vs RFREQ performance curve shows

the variation of line rate with RFREQ.

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