AD7715AR-5(RevC) 데이터 시트보기 (PDF) - Analog Devices
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AD7715AR-5 Datasheet PDF : 31 Pages
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AD7715-5–SPECIFICATIONS (AVDD = +5␣ V, DVDD = +3␣ V or +5␣ V, REF IN(+) = +2.5␣ V; REF␣ IN(–) = AGND;
fCLK IN = 2.4576␣ MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
A Version1
Unit
Conditions/Comments
STATIC PERFORMANCE
No Missing Codes
Output Noise
Integral Nonlinearity
Unipolar Offset Error
Unipolar Offset Drift3
Bipolar Zero Error
Bipolar Zero Drift3
Positive Full-Scale Error4
Full-Scale Drift3, 5
Gain Error6
Gain Drift3, 7
Bipolar Negative Full-Scale Error2
Bipolar Negative Full-Scale Drift3
16
See Tables V to VIII
± 0.0015
See Note 2
0.5
See Note 2
0.5
See Note 2
0.5
See Note 2
0.5
± 0.0015
1
0.6
Bits min
% of FSR max
µV/°C typ
µV/°C typ
µV/°C typ
ppm of FSR/°C typ
% of FSR max
µV/°C typ
µV/°C typ
Guaranteed by Design. Filter Notch ≤ 60␣ Hz
Depends on Filter Cutoffs and Selected Gain
Filter Notch ≤ 60␣ Hz
Typically ±0.0004%
For Gains of 1 and 2
For Gains of 32 and 128
ANALOG INPUTS/REFERENCE INPUTS
Input Common-Mode Rejection (CMR)
Normal-Mode 50 Hz Rejection8
Normal-Mode 60 Hz Rejection8
Common-Mode 50 Hz Rejection8
Common-Mode 60 Hz Rejection8
Common-Mode Voltage Range9
Absolute AIN/REF IN Voltage8
Absolute/Common-Mode AIN Voltage9
AIN DC Input Current8
AIN Sampling Capacitance8
AIN Differential Voltage Range10
AIN Input Sampling Rate, fS
REF IN(+) – REF IN(–) Voltage
REF IN Input Sampling Rate, fS
90
98
98
150
150
AGND to AVDD
AGND – 30 mV
AVDD + 30␣ mV
AGND + 50␣ mV
AVDD – 1.5␣ V
1
10
0 to +VREF/GAIN11
± VREF/GAIN
GAIN × fCLK␣ IN/64
fCLK␣ IN/8
+2.5
dB min
dB min
dB min
dB min
dB min
V min to V max
V min
V max
V min
V max
nA max
pF max
nom
nom
V nom
fCLK IN/64
Specifications for AIN and REF IN Unless Noted
at DC. Typically 102 dB
For Filter Notches of 25 Hz, 50 Hz, ± 0.02 × fNOTCH
For Filter Notches of 20 Hz, 60 Hz, ± 0.02 × fNOTCH
For Filter Notches of 25 Hz, 50 Hz, ± 0.02 × fNOTCH
For Filter Notches of 20 Hz, 60 Hz, ± 0.02 × fNOTCH
AIN for BUF Bit of Setup Register = 0 and REF IN
AIN for BUF Bit of Setup Register = 0 and REF IN
BUF Bit of Setup Register = 1
Unipolar Input Range (B/U Bit of Setup Register = 1)
Bipolar Input Range (B/U Bit of Setup Register = 0)
For Gains of 1 and 2
For Gains of 32 and 128
±1% for Specified Performance. Functional with
Lower VREF
LOGIC INPUTS
Input Current
± 10
All Inputs Except MCLK IN
VINL, Input Low Voltage
0.8
VINL, Input Low Voltage
0.4
VINH, Input High Voltage
2.4
VINH, Input High Voltage
2.0
MCLK IN Only
VINL, Input Low Voltage
0.8
VINL, Input Low Voltage
0.4
VINH, Input High Voltage
3.5
VINH, Input High Voltage
2.5
µA max
V max
V max
V min
V min
V max
V max
V min
V min
DVDD = +5␣ V
DVDD = +3.3␣ V
DVDD = +5 V
DVDD = +5␣ V
DVDD = +3.3␣ V
DVDD = +5␣ V
DVDD = +3.3␣ V
LOGIC OUTPUTS (Including MCLK OUT)
VOL, Output Low Voltage
VOL, Output Low Voltage
VOH, Output High Voltage
VOH, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance13
Data Output Coding
0.4
0.4
4.0
DVDD – 0.6 V
± 10
9
Binary
Offset Binary
V max
V max
V min
V min
µA max
pF typ
ISINK = 800␣ µA Except for MCLK OUT12. DVDD = +5␣ V
ISINK = 100␣ µA Except for MCLK OUT12. DVDD = +3.3␣ V
ISOURCE = 200 µA Except for MCLK OUT12. DVDD = +5␣ V
ISOURCE = 100 µA Except for MCLK OUT12. DVDD = +3.3␣ V
Unipolar Mode
Bipolar Mode
–2–
REV. C
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