EBE21AD4AJFA-6E-E 데이터 시트보기 (PDF) - Elpida Memory, Inc
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EBE21AD4AJFA-6E-E Datasheet PDF : 28 Pages
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EBE21AD4AJFA
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0
Number of bytes utilized by module
manufacturer
1 0 0 0 0 0 0 0 80H
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
2
Memory type
0 0 0 0 1 0 0 0 08H
3
Number of row address
0 0 0 0 1 1 1 0 0EH
4
Number of column address
0 0 0 0 1 0 1 1 0BH
5
Number of DIMM ranks
0 1 1 0 0 0 0 1 61H
6
Module data width
0 1 0 0 1 0 0 0 48H
7
Module data width continuation
0 0 0 0 0 0 0 0 00H
8
Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
9
DDR SDRAM cycle time, CL = 5
0 0 1 1 0 0 0 0 30H
10
SDRAM access from clock (tAC)
0 1 0 0 0 1 0 1 45H
11
DIMM configuration type
0 0 0 0 0 1 1 0 06H
12
Refresh rate/type
1 0 0 0 0 0 1 0 82H
13
Primary SDRAM width
0 0 0 0 0 1 0 0 04H
14
Error checking SDRAM width
0 0 0 0 0 1 0 0 04H
15
Reserved
0 0 0 0 0 0 0 0 00H
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
18
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
19
DIMM Mechanical Characteristics
0 0 0 0 0 0 0 1 01H
20
DIMM type information
0 0 0 0 0 0 0 1 01H
21
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
22
SDRAM device attributes: General
0 0 0 0 0 0 1 1 03H
23
Minimum clock cycle time at CL = 4
0 0 1 1 1 1 0 1 3DH
24
Maximum data access time (tAC) from
clock at CL = 4
0
1
0
1
0
0
0
0
50H
25
Minimum clock cycle time at CL = 3
0 1 0 1 0 0 0 0 50H
26
Maximum data access time (tAC) from
clock at CL = 3
0
1
1
0
0
0
0
0
60H
27
Minimum row precharge time (tRP)
0 0 1 1 1 1 0 0 3CH
28
Minimum row active to row active delay
(tRRD)
0
0
0
1
1
1
1
0
1EH
29
Minimum /RAS to /CAS delay (tRCD) 0 0 1 1 1 1 0 0 3CH
30
Minimum active to precharge time
(tRAS)
0 0 1 0 1 1 0 1 2DH
31
Module rank density
0 0 0 0 0 0 0 1 01H
32
Address and command setup time
before clock (tIS)
0 0 1 0 0 0 0 0 20H
33
Address and command hold time after
clock (tIH)
0
0
1
0
0
1
1
1
27H
34
Data input setup time before clock (tDS) 0 0 0 1 0 0 0 0 10H
35
Data input hold time after clock (tDH) 0 0 0 1 0 1 1 1 17H
Comments
128 bytes
256 bytes
DDR2 SDRAM
14
11
2
72
0
SSTL 1.8V
3.0ns*1
0.45ns*1
ECC, Address/
Command Parity
7.8µs
×4
×4
0
4, 8
4
3, 4, 5
4.00mm max.
Registered
Normal
Weak Driver
50Ω ODT Support
3.75ns*1
0.5ns*1
5.0ns*1
0.6ns*1
15ns
7.5ns
15ns
45ns
1GB
0.20ns*1
0.27ns*1
0.10ns*1
0.17ns*1
Data Sheet E1041E30 (Ver. 3.0)
5
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