EBE21FD4AHFT, EBE21FD4AHFE, EBE21FD4AHFL
AMB Component Timing
For purposes of IDD testing, the following parameters are to be utilized.
Parameter
EI Assertion pass-thru timing
EI deassertion pass-thru timing
Symbol
tEI
propagate
tEID
min.
typ.
—
—
—
—
EI assertion duration
Resample pass-thru time
tEI
100
—
—
TBD
Resynch pass-thru Time
—
TBD
Bit lock Interval
tBitLock
—
—
Frame lock Interval
tFrameLock
—
—
Note: 1. The EI stands for ″Electrical Idle″.
max.
4
bit lock
—
—
—
119
154
Units
clks
clks
clks
ns
ns
frames
frames
Note
Power Specification Parameter and Test Conditions
Frequency (Mbps)
Parameter
Symbol
Idle Current,
single or last
DIMM
Idd_Idle_0
Idle Current, first
DIMM
Idd_Idle_1
Power
Supply
@1.5V
@1.8V
Total
@1.5V
@1.8V
Total
-6E -5C
667 533
max. max. Unit Conditions
Note
2.60 2.20 A
2.58 2.34 A
8.14 7.05 W
L0 state, idle (0 BW)
Primary channel enabled,
Secondary channel disabled
CKE high. Command and address lines stable.
DRAM clock active.
3.40 3.00 A
2.57 2.33 A
9.37 8.30 W
L0 state, idle (0 BW)
Primary and secondary channels enabled
CKE high. Command and address lines stable.
DRAM clock active.
Active Power
@1.5V
Idd_Active_1 @1.8V
Total
Active Power,
data pass through
Idd_Active_2
@1.5V
@1.8V
Total
Training
@1.5V
Idd_Training
(for AMB spec. @1.8V
Not in SPD)
Total
3.90 3.40 A
4.82 4.68 A
14.44 13.39 W
3.70 3.20 A
2.20 2.01 A
9.14 8.01 W
4.00 3.50 A
2.39 2.18 A
9.99 8.81 W
L0 state
50% DRAM BW, 67% read, 33% write.
Primary and secondary channels enabled.
DRAM clock active, CKE high.
L0 state
50% DRAM BW to downstream DIMM,
67% read, 33% write.
Primary and secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active.
Primary and secondary channels enabled.
100% toggle on all channel lanes
DRAMs idle. 0 BW.
CKE high, Command and address lines stable.
DRAM clock active.
Preliminary Data Sheet E1001E30 (Ver. 3.0)
11