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전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크

EDE1108ACBG-6E-E 데이터 시트보기 (PDF) - Elpida Memory, Inc

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EDE1108ACBG-6E-E
Elpida
Elpida Memory, Inc Elpida
EDE1108ACBG-6E-E Datasheet PDF : 29 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
EBE10UE8ACWA
Byte No.
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Maximum data access time (tAC)
from clock at CL = X 2
0 1 1 0 0 0 0 0 60H
-8E, -6E (CL = 3)
-8G (CL = 4)
0 1 0 1 0 0 0 0 50H
Minimum row precharge time (tRP)
-8E
0
0
1
1
0
0
1
0
32H
-8G, -6E
0 0 1 1 1 1 0 0 3CH
Minimum row active to row active
delay (tRRD)
00
01
11
10
1EH
Minimum /RAS to /CAS delay (tRCD)
-8E
0
0
1
1
0
0
1
0
32H
-8G, -6E
0 0 1 1 1 1 0 0 3CH
Minimum active to precharge time
(tRAS)
0
0
1
0
1
1
0
1
2DH
Module rank density
0 0 0 0 0 0 0 1 01H
Address and command setup time
before clock (tIS)
0 0 0 1 0 1 1 1 17H
-8E, -8G
-6E
0 0 1 0 0 0 0 0 20H
0.6ns*1
0.5ns*1
12.5ns
15ns
7.5ns
12.5ns
15ns
45ns
1G bytes
0.17ns*1
0.20ns*1
Address and command hold time
after clock (tIH)
-8E, -8G
0 0 1 0 0 1 0 1 25H
-6E
0 0 1 0 0 1 1 1 27H
Data input setup time before clock
(tDS)
0 0 0 0 0 1 0 1 05H
-8E, -8G
-6E
0 0 0 1 0 0 0 0 10H
0.25ns*1
0.27ns*1
0.05ns*1
0.10ns*1
Data input hold time after clock (tDH)
-8E, -8G
0
0
0
1
0
0
1
0
12H
-6E
0 0 0 1 0 1 1 1 17H
Write recovery time (tWR)
0 0 1 1 1 1 0 0 3CH
Internal write to read command delay
(tWTR)
0
0
0
1
1
1
1
0
1EH
Internal read to precharge command
delay (tRTP)
0
0
0
1
1
1
1
0
1EH
Memory analysis probe
characteristics
0 0 0 0 0 0 0 0 00H
Extension of Byte 41 and 42
-8E
0 0 1 1 0 1 1 0 36H
-8G, -6E
0 0 0 0 0 1 1 0 06H
0.12ns*1
0.17ns*1
15ns*1
7.5ns*1
7.5ns*1
TBD
Active command period (tRC)
-8E
0 0 1 1 1 0 0 1 39H
-8G, -6E
0 0 1 1 1 1 0 0 3CH
Auto refresh to active/
Auto refresh command cycle (tRFC)
0
1
1
1
1
1
1
1
7FH
SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0 80H
Dout to DQS skew
-8E, -8G
0 0 0 1 0 1 0 0 14H
-6E
0 0 0 1 1 0 0 0 18H
Data hold skew (tQHS)
-8E, -8G
0 0 0 1 1 1 1 0 1EH
-6E
0 0 1 0 0 0 1 0 22H
57.5ns*1
60ns*1
127.5ns*1
8ns*1
0.20ns*1
0.24ns*1
0.30ns*1
0.34ns*1
PLL relock time
0 0 0 0 0 0 0 0 00H
Undefined
Data Sheet E1226E10 (Ver. 1.0)
6

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