EBD11UD8ABDA-7B 데이터 시트보기 (PDF) - Elpida Memory, Inc
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EBD11UD8ABDA-7B Datasheet PDF : 19 Pages
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EBD11UD8ABDA
Block Diagram
/CS1
/CS0
DQS0
DM0
DQ0 to DQ7
DQS1
DM1
DQ8 to DQ15
RS
RS
8 RS
RS
RS
8 RS
DQS /CS
DM D0
I/O0 to I/O7
DQS /CS
DM D1
I/O0 to I/O7
DQS /CS
DM D8
I/O0 to I/O7
DQS /CS
DM D9
I/O0 to I/O7
DQS4
DM4
DQ32 to DQ39
DQS5
DM5
DQ40 to DQ47
RS
RS
8 RS
RS
RS
8 RS
DQS /CS
DM D4
I/O0 to I/O7
DQS /CS
DM D5
I/O0 to I/O7
DQS /CS
DM D12
I/O0 to I/O7
DQS /CS
DM D13
I/O0 to I/O7
DQS2
DM2
DQ16 to DQ23
DQS3
DM3
DQ24 to DQ31
RS
RS
8 RS
RS
RS
8 RS
/CS
DQS
DM D2
I/O0 to I/O7
DQS /CS
DM D3
I/O0 to I/O7
/CS
DQS
DM D10
I/O0 to I/O7
DQS /CS
DM D11
I/O0 to I/O7
DQS6
DM6
DQ48 to DQ55
DQS7
DM7
DQ56 to DQ63
RS
RS
8 RS
RS
RS
8 RS
DQS /CS
DM D6
I/O0 to I/O7
DQS /CS
DM D7
I/O0 to I/O7
DQS /CS
DM D14
I/O0 to I/O7
DQS /CS
DM D15
I/O0 to I/O7
Serial PD
BA0 to BA1
A0 to AN
/RAS
/CAS
/WE
CKE0
CKE1
VDDSPD
VREF
VDD
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D7)
SDRAMs (D8 to D15)
SPD
SDRAMs (D0 to D15)
SDRAMs (D0 to D15), VDD and VDDQ
VSS
VDDID
Open
SDRAMs (D0 to D15), SPD
SDRAMs (D0 to D15), SPD
* D0 to D15 : 512M bits DDR SDRAM
U0 : 2k bit EEPROM
Rs : 22Ω
SCL
SCL
SDA
SDA
SA0
A0 U0
SA1
A1
SA2
A2 WP
CK0
/CK0
CK1
/CK1
CK2
/CK2
8 loads
8 loads
0 loads
Notes :
1. DQ wiring may differ from that described
in this drawing; however DQ/DM/DQS
relationships are maintained as shown.
VDDID strap connections:
(for memory device VDD, VDDQ)
Strap out (open): VDD = VDDQ
Strap in (closed): VDD ≠ VDDQ
2. The SDA pull-up registor is reguired due to
the open-drain/open-collector output.
3. The SCL pull-up registor is recommended,
because of the normal SCL lime inactive
"high" state.
Data Sheet E0287E70 (Ver. 7.0)
8
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