CXB1561Q-Y 데이터 시트보기 (PDF) - Sony Semiconductor

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CXB1561Q-Y

s3R-IC for Optical Fiber Cimmunication Receiver

Sony Semiconductor 

CXB1561Q-Y

Description of Operation

1. Overall operations

The structure of optical-fiber communication receiver system is shown in Fig. 1. The CXB1561Q-Y performs

the 3R operations indicated below.

• Photodiode .........Converts a data optical signal to a current signal.

• Pre Amp..............Converts a data current signal to a voltage signal (however, the voltage level is feeble).

• 3R .......................1) Amplifies a feeble data voltage signal (Reshaping).

2) Outputs a data signal in sync with a clock signal (Retiming).

3) Outputs both data and clock signals as ECL level signals (Regenerating).

Optical signal Vcc

Pre Amp

3R

Current signal

Voltage signal

Data signal

Clock signal

Fig. 1. Optical fiber communication receiver system clock

The signal flow of the CXB1561Q-Y, including the SAW filter, is as shown in Fig. 2. First, the feeble signal

output of the pre-amplifier enters the post-amplifier and is amplified to an IC internal logic level. The amplified

signal is then divided into the clock and data sides shown below. The clock side derives a clock signal from a

data signal. First, the post-amplifier signal enters the differentiator, which generates a pulse output having an

uniform width at the signal rise and fall times. This output pulse enters the SAW filter, which generates

resonance at regular intervals and outputs a SIN wave having a resonance frequency. This signal output then

enters the limiter amplifier and is amplified to an IC internal logic level. This amplified signal is used as the D-

FF block clock signal. In the data side, on the other hand, the post-amplifier signal enters the delay section,

where the signal is delayed to accomplish data/clock synchronization at the D-FF block. The signals separated

into the clock and data sides are therefore synchronized with each other at the D-FF block and output to the

outside.

Feeble signal

(from pre-amplifier)

Post-amplifier

Clock side

Differentiator

SAW

Limit Amplifier

Delay

Data side

Fig. 2. Signal flow

D-FF

Data output

Clock signal

– 11 –

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