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S1M8836

FRACTIONAL-N RF/INTEGER-N IF DUAL PLL

Samsung 

FRACTIONAL-N RF/INTEGER-N IF DUAL PLL

S1M8836/37

PIN DESCRIPTION

Pin No. Symbol I/O

Descriptions

1

VDDRF – RF PLL power supply (2.7V to 4.0V). Must be equal to VDDIF.

2

VpRF – Power supply for RF charge pump. Must be ≥ VDDRF and VDDIF.

3

CPoRF O RF charge pump output. Connected to an external loop filter.

4

DGND – Ground for RF PLL digital circuitry.

5

finRF I RF prescaler input. Small signal input from the external VCO.

I RF prescaler complementary input. For a single-ended output RF VCO, a bypass

6

finRF

capacitor should be placed as close as possible to this pin and be connected

directly to the ground plane.

7

GNDRF – Ground for RF PLL analog circuitry.

8

VDDRFa – PLL power supply (2.7V to 4.0V) for RF analog (prescaler). Must be equal to VDDRF

9

OSCin I Oscillator input to drive both the IF and RF R counter inputs.

10

foLD O Multiplexed output of N or R divider and RF/IF lock detect.

11 RF_EN I RF PLL Enable (Enable when HIGH, Power down when LOW). Controls the RF PLL

to power down directly, not depending on a program control. Also sets the charge

pump output to be in TRI-STATE when LOW. Powers up when HIGH depends on

the state of RF_CTL_WORD.

12

IF_EN I IF PLL Enable (Enable when HIGH, Power-down when LOW). Controls the IF PLL

to power down directly. The same as RF_EN except that power-up depends on the

state of IF_CTL_WORD.

13 CLOCK I CMOS clock input. Data for the various counters is clocked into the 22-bit shift

register on the rising edge.

14

DATA I Binary serial data input. Data entered MSB (Most Significant Bit) first.

15

LE

I Load enable when LE goes HIGH. High impedance CMOS input.

16

GNDIF – Ground for IF analog circuitry.

17

finIF I IF prescaler complementary input. For a single-ended output IF VCO, a bypass

capacitor should be placed as close as possible to this pin.

18

finIF I IF prescaler input. Small signal input from the VCO.

19

DGND – Ground for IF PLL digital circuitry.

20

CPoIF O IF charge pump output. Connected to an external loop filter.

21

VpIF – Power supply for IF charge pump. Must be ≥ VDDRF and VDDIF.

22

VDDIF – IF PLL power supply (2.7V to 4.0V). Must be equal to VDDRF.

23

OUT1 O Programmable CMOS output. Level of the output is controlled by W2[19] bit.

24

OUT0 O Programmable CMOS output. Level of the output is controlled by W2[18] bit.

In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous

switches between active low and tri-state.

5

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