DS4000 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS4000 Datasheet PDF : 19 Pages
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DS4000 Digitally Controlled TCXO
AC ELECTRICAL CHARACTERISTICS—2-WIRE SERIAL INTERFACE
(VCC = 4.75 to 5.25V, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITION
MIN
TYP MAX
SCL Clock Frequency
Fast mode
fSCL
Standard mode
0
400
0
100
Bus Free Time Between
Fast mode
1.3
a STOP and START
tBUF
Condition
Standard mode
4.7
Hold Time (Repeated)
START Condition
tHD:STA
Fast mode (Note 7)
Standard mode (Note 7)
0.6
4.0
Low Period of SCL
Clock
Fast mode
tLOW
Standard mode
1.3
4.7
UNITS
kHz
ms
ms
ms
High Period of SCL
Clock
Setup Time for a
Repeated START
Condition
Data Hold Time
Data Setup Time
Fast mode
0.6
tHIGH
Standard mode
4.0
Fast mode
0.6
tSU:STA
Standard mode
4.7
Fast mode (Note 8)
0
tHD:DAT
Standard mode (Note 8)
0
Fast mode (Note 9)
100
tSU:DAT
Standard mode (Note 9)
250
ms
ms
0.9
ms
0.9
ns
Rise Time of Both SDA
and SCL
Fall Time of Both SDA
and SCL
Fast mode (Note 9)
20 + 0.1CB
tR
Standard mode (Note 9)
20 + 0.1CB
Fast mode (Note 10)
20 + 0.1CB
tF
Standard mode (Note 10) 20 + 0.1CB
300
ns
1000
300
ns
1000
Setup Time for STOP
Condition
tSU:STO
Fast mode
0.6
ms
Standard mode
4.0
Capacitive Load for
Each Bus Line
CB
(Note 10)
400
pF
Input Capacitance
CI
5
pF
Note 7: After this period, the first clock pulse is generated.
Note 8: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 9: A fast-mode device can be used in a standard mode system, but the requirement tSU:DAT >250ns must then be met. This is automatically
the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL
signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT (1000 + 250 = 1250ns) before the SCL line is released.
Note 10: CB: Total capacitance of one bus line in pF.
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