DS2401
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 5
RESISTOR
MASTER
DS2401
480μs ≤ tRSTL < ∞ *
480μs ≤ tRSTH < ∞ (includes recovery time)
15μs ≤ tPDH < 60μs
60μs ≤ tPDL < 240μs
∗ In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always
be less than 960μs.
READ/WRITE TIMING DIAGRAM Figure 6
Write-One Time Slot
RESISTOR
MASTER
60μs ≤ tSLOT < 120μs
1μs ≤ tLOW1 < 15μs
1μs ≤ tREC < ∞
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