DS2401_06 데이터 시트보기 (PDF) - Maxim Integrated

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DS2401_06

Silicon Serial Number

Maxim Integrated 

NOTES:

1) All voltages are referenced to ground.

DS2401

2) VPUP = external pullup voltage.

3) Input load is to ground.

4) An additional reset or communication sequence cannot begin until the reset high time has expired.

5) Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is

guaranteed to be valid within 1μs of this falling edge and will remain valid for 14μs minimum (15μs

total from falling edge on 1-Wire bus).

6) VIH is a function of the external pullup resistor and the VCC supply.

7) 30 nanocoulombs per 72 time slots @ 5.0V.

8) At VCC = 5.0V with a 5kΩ pullup to VCC and a maximum time slot of 120μs.

9) Capacitance on the I/O pin could be 800pF when power is first applied. If a 5kΩ resistor is used to

pullup the I/O line to VCC, 5μs after power has been applied the parasite capacitance will not affect

normal communications.

10) The reset low time (tRSTL) should be restricted to a maximum of 960μs, to allow interrupt signaling,

otherwise it could mask or conceal interrupt pulses if this device is used in parallel with a DS2404 or

DS1994.

11) The optimal sampling point for the master is as close as possible to the end time of the tRDV period

without exceeding tRDV. For the case of a Read-One Time slot, this maximizes the amount of time for

the pullup resistor to recover to a high level. For a Read-Zero Time slot, it ensures that a read will

occur before the fastest 1-Wire device(s) releases the line.

12) The duration of the low pulse sent by the master should be a minimum of 1μs with a maximum value

as short as possible to allow time for the pullup resistor to recover the line to a high level before the 1-

Wire device samples in the case of a Write-One Time or before the master samples in the case of a

Read-One Time.

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