D8259 데이터 시트보기 (PDF) - Digital Core Design
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D8259 Datasheet PDF : 4 Pages
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DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environ-
ment
◊ Active-HDL automatic simulation mac-
ros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, mi-
nor and major versions changes
● Delivery the documentation up-
dates
● Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of
IP Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implemen-
tation.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA
bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restric-
tion except One Year license where time of
use is limited to 12 months.
● Single Design license for
○ VHDL, Verilog source code called HDL
Source
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
○ Encrypted Netlist only
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ HDL Source to Netlist
○ Single Design to Unlimited Designs
SYMBOL
rst
datai(7:0) datao(7:0)
a0
dbe
cs
rd
wr
ir(7:0)
inta
casi(2:0)
int
caso(2:0)
case
sp
en
PINS DESCRIPTION
PIN TYPE
DESCRIPTION
rst
input Power-up reset
datai(7:0) input Data bus (input)
a0
input Processor address line
cs
input Chip select
rd
input Read strobe
wr
input Write strobe
ir(7:0)
input Interrupt request lines
inta
input Interrupt acknowledge
casi(2:0) input Cascade input lines
sp
input Slave program input
datao(7:0) output Data bus (output)
dbe
output Data bus output enable
int
output Interrupt request output
caso(2:0) output Cascade output lines
case
output Cascade output enable
en
output Buffer transceiver enable
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
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