CY7C4205V 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C4205V

64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs

Cypress Semiconductor 

Switching Waveforms (continued)

Programmable Almost Full Flag Timing

WCLK

tCLKH

WEN

[25]

PAF

RCLK

REN

CY7C4225V/4205V/4215V

CY7C4425V/4235V/4245V

Note 24

tCLKL

tENS tENH

tPAF

FULL − M WORDS

IN FIFO [26]

FULL − (M + 1) WORDS

IN FIFO [27]

tPAF

tENS

Programmable Almost Full Flag Timing (applies only in SMODE (SMODE in LOW))

WCLK

tCLKH

WEN

PAF

RCLK

REN

tCLKL

tENS tENH

FULL – (M + 1) WORDS

IN FIFO

Note 28

Note 29 tPAF

FULL − M WORDS

IN FIFO[26]

tSKEW3[30]

tENS

tENS tENH

tPAFsynch

Notes:

24. PAF offset = m. Number of data words written into FIFO already = 64 − m + 1 for the CY7C4425V, 256 − m + 1 for the CY7C4205V, 512 − m + 1 for the CY7C4215V.

1024 − m + 1 for the CY7C4225V, 2048 − m + 1 for the CY7C4235V, and 4096 − m + 1 for the CY7C4245V.

25. PAF is offset = m.

26. 64 − m words in CY7C4425V, 256 – m words inCY7C4205V, 512 − m words in CY7C4215V. 1024 – m words in CY7C4225V, 2048 − m words in CY7C4235V,

and 4096 – m words in CY7C4245V.

27. 64 − m + 1 words in CY7C4425V, 256 − m + 1 words in CY7C4205V, 512 − m +1 words in CY7C4215V, 1024 − m + 1 CY7C4225V, 2048 − m + 1 in CY74235V,

and 4096 − m + 1 words in CY7C4245V.

28. If a write is performed on this rising edge of the write clock, there will be Full – (m–1) words of the FIFO when PAF goes LOW.

29. PAF offset = m.

30. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of

RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge.

Document #: 38-06029 Rev. *C

Page 15 of 20

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