CY7C265-25(2006) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C265-25
(Rev.:2006)

8K x 8 Registered PROM

Cypress Semiconductor 

CY7C265

respect to power-up and power-down during intelligent

programming also apply during architecture programming.

Once the supervoltages have been established and the

correct logic states exist on the other device pins,

programming may begin. Programming is accomplished by

pulling PGM from HIGH to LOW and then back to HIGH with

a pulse width equal to 10 ms.

Table 1. Mode Selection

Read or Output Disable

Mode

Other

Asynchronous Enable Read

Synchronous Enable Read

Asynchronous Initialization Read

Program Memory

Program Verify

Program Inhibit

Program Synchronous Enable

Program Initialize

Program Initial Byte

A12

A12

A12

A12

A12

A12

A12

A12

VIHP

VILP

A12

A11

A11

A11

A11

A11

A11

A11

A11

VIHP

VIHP

VILP

Pin Function

A10–A7

A10–A7

A10–A7

A10–A7

A10–A7

A10–A7

A10–A7

A10–A7

A10–A7

A10–A7

A10 – A7

A6

A5

A6

A5

A6

A5

A6

A5

A6

A5

A6

A5

A6

A5

A6

A5

VIHP

VPP

VIHP

VPP

VIHP

VPP

A4–A3

A4–A3

A4–A3

A4–A3

A4–A3

A4–A3

A4–A3

A4–A3

A4–A3

A4–A3

A4–A3

A2

A2

A2

A2

A2

A2

A2

A2

VIHP

VILP

VILP

Read or Output Disable

Mode

Other

Asynchronous Enable Read

Synchronous Enable Read

Asynchronous Initialization Read

Program Memory

Program Verify

Program Inhibit

Program Synchronous Enable

Program Initialize

Program Initial Byte

A1

A0

A1

A0

A1

A0

A1

A0

A1

A0

A1

A0

A1

A0

A1

A0

VPP VILP

VPP VILP

VPP VIHP

GND

PGM

GND

GND

GND

VILP

VIHP

VIHP

VILP

VILP

VILP

Pin Function

CLK

GND

CLK

VFY

VIL

VIL/VIH

VIL

VILP

VILP

VILP

VILP

VILP

VILP

GND

GND

GND

VIHP

VILP

VIHP

VIHP

VIHP

VIHP

E, I

O7–O0

VPP

D7–D0

VIL

O7–O0

VIL

O7–O0

VIL

O7–O0

VPP

D7–D0

VPP

O7–O0

VPP

High Z

VPP

D7–D0

VPP

D7–D0

VPP

D7–D0

Document #: 38-04012 Rev. *B

Page 6 of 13

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