24AA32-/SN 데이터 시트보기 (PDF) - Microchip Technology
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24AA32-/SN Datasheet PDF : 12 Pages
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24AA32
6.3 Contiguous Addressing Across
Multiple Devices
The device select bits A2, A1, A0 can be used to
expand the contiguous address space for up to 256K
bits by adding up to eight 24AA32's on the same bus.
In this case, software can use A0 of the control byte as
address bit A12, A1 as address bit A13, and A2 as
address bit A14.
6.4 Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24AA32 transmits the
first data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24AA32 to transmit the
next sequentially addressed 8 bit word (Figure 6-3).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a stop condition.
To provide sequential reads the 24AA32 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation. The address pointer, however,
will not roll over from address 07FF to address 0000. It
will roll from 07FF to unused memory space.
6.5 Noise Protection
The SCL and SDA inputs have filter circuits which sup-
press noise spikes to ensure proper device operation
even on a noisy bus. All I/O lines incorporate Schmitt
triggers for 400 kHz (Fast Mode) compatibility.
FIGURE 6-2: RANDOM READ
S
T
A
CONTROL
R
BYTE
T
WORD
ADDRESS (1)
WORD
ADDRESS (0)
S
T
A
CONTROL
R
BYTE
T
S
DATA n
T
O
P
SDA LINE
0000
BUS
ACTIVITY:
A
A
A
C
C
C
K
K
K
A
N
C
O
K
A
C
K
FIGURE 6-3: SEQUENTIAL READ
Bus Activity:
Master
SDA Line
Bus Activity
Control
Byte
A
C
K
Data n
Data n + 1
Data n + 2
A
A
A
C
C
C
K
K
K
S
t
Data n + X
o
p
N
O
A
C
K
DS21124C-page 8
© 1996 Microchip Technology Inc.
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