CY7C149(1993) 데이터 시트보기 (PDF) - Cypress Semiconductor
부품명
상세내역
일치하는 목록
CY7C149 Datasheet PDF : 8 Pages
| |||
CY7C148
CY7C149
AC Test Loads and Waveforms
5V
OUTPUT
R1481 Ω
5V
OUTPUT
R1481 Ω
30 pF
R2
255Ω
INCLUDING
JIG AND
SCOPE (a)
5 pF
INCLUDING
JIG AND
SCOPE (b)
R2
255Ω
C148–4
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
3.0V
GND
< 10 ns
ALL INPUT PULSES
90%
10%
90%
10%
< 10 ns
C148–5
Switching Characteristics Over the Operating Range[2]
7C148−25
7C149−25
7C148−35
7C149−35
7C148−45
7C149−45
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Address Valid to Address Do Not Care Time
25
35
45
ns
(Read Cycle Time)
tAA
Address Valid to Data Out Valid Delay
(Address Access Time)
25
35
tACS1
Chip Select LOW to Data Out Valid (7C148 only)
25[6]
35
tACS2
30[7]
35
45
ns
45
ns
45
ns
tACS
tLZ[8]
Chip Select LOW to Data Out Valid (7C149 only)
Chip Select LOW to Data Out On
7C148 8
7C149 5
tHZ[8]
Chip Select HIGH to Data Out Off
0
tOH
Address Unknown to Data Out Unknown Time
0
tPD
Chip Select HIGH to Power-Down Delay 7C148
tPU
Chip Select LOW to Power-Up Delay
7C148 0
WRITE CYCLE
15
15
20
ns
10
10
ns
5
5
15
0
20
0
20
ns
0
5
ns
20
30
30
ns
0
0
ns
tWC
Address Valid to Address Do Not Care
(Write Cycle Time)
25
35
45
ns
tWP[9]
Write Enable LOW to Write Enable HIGH
20
30
35
ns
tWR
tWZ[8]
Address Hold from Write End
Write Enable to Output in High Z
5
5
5
ns
0
8
0
8
0
8
ns
tDW
Data in Valid to Write Enable HIGH
12
20
20
ns
tDH
Data Hold Time
0
0
0
ns
tAS
Address Valid to Write Enable LOW
0
0
0
ns
tCW[9]
Chip Select LOW to Write Enable HIGH
20
30
40
ns
tOW[8]
Write Enable HIGH to Output in Low Z
0
0
0
ns
tAW
Address Valid to End of Write
20
30
35
ns
Notes:
6. Chip deselected greater than 25 ns prior to selection.
7. Chip deselected less than 25 ns prior to selection.
8. At any given temperature and voltage condition, tHZ is less than tLZ for all devices. Transition is measured ±500 mV from steady-state voltage with specified
loading in part (b) of AC Test Loads.
9. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
Share Link: 