AD8108AST 데이터 시트보기 (PDF) - Analog Devices
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AD8108AST Datasheet PDF : 33 Pages
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AD8108/AD8109
Table 6. Operation Truth Table
CE UPDATE CLK DATA IN
1X
XX
01
f
Datai
DATA OUT
X
Datai-32
RESET
X
1
SER/
PAR
X
0
01
00
XX
f
D0 … D3, NA in parallel 1
1
A0 … A2 mode
X X…
X
1
X
XX
X
0
X
Operation/Comment
No change in logic.
The data on the serial DATA IN line is loaded into serial register. The
first bit clocked into the serial register appears at DATA OUT 32 clocks
later.
The data on the parallel data lines, D0 to D3, are loaded into the
32-bit serial shift register location addressed by A0 to A2.
Data in the 32-bit shift register transfers into the parallel latches that
control the switch array. Latches are transparent.
Asynchronous operation. All outputs are disabled. Remainder of logic
is unchanged.
D0
PARALLEL DATA D1
D2
(OUTPUT ENABLE) D3
SER/PAR
DATA IN
(SERIAL)
S
D1
Q
D0
DQ
CLK
S
D1
Q
D0
DQ
CLK
S
D1
Q
D0
DQ
CLK
S
D1
Q DQ
D0 CLK
S
D1
Q
D0
DQ
CLK
S
D1
Q
D0
DQ
CLK
S
D1
Q
D0
DQ
CLK
S
D1
Q
D0
DQ
CLK
S
D1
Q
D0
DQ
CLK
S
D1
Q
D0
DQ
CLK
DATA
OUT
CLK
CE
RESET
OUT0 EN
OUT1 EN
OUT2 EN
A0
OUT3 EN
A1
OUT4 EN
A2
OUT5 EN
OUT6 EN
OUT7 EN
LE D
OUT0
B0
Q
LE D
OUT0
B1
Q
LE D
OUT0
B2
Q
LE D
OUT0
EN
CLR Q
LE D
OUT1
B0
Q
LE D
OUT6
EN
CLR Q
LE D
OUT7
B0
Q
LE D
OUT7
B1
Q
LE D
OUT7
B2
Q
LE D
OUT7
EN
CLR Q
64
SWITCH MATRIX
DECODE
Figure 4. Logic Diagram
8
OUTPUT ENABLE
Rev. B | Page 7 of 32
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