7C1360A-150 데이터 시트보기 (PDF) - Cypress Semiconductor

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7C1360A-150

256K x 36/512K x 18 Synchronous Pipelined Burst SRAM

Cypress Semiconductor 

CY7C1360A

CY7C1362A

Functional Block Diagram—256K × 36[1]

BBWWaa

BBWWEE

CLCKLK

BBWbb

GGWW

BBWWcc

BYTE a WRITE

DQ

BYTE b WRITE

DQ

BYTE c WRITE

DQ

BBWdd

BYTE d WRITE

DQ

CCEE1

CCEE22

CCEE23

OOEE

ZZZZ

AADDSPSP

AA

ADASDCSC

ENABLE

DQ

DQ

Power Down Logic

16

Address

Register

Input

Register

AADDVV

AA01--AA10

MMODDEE

CLR

Binary

Counter

& Logic

Functional Block Diagram—512K × 18[1]

OUTPUT

REGISTER

DQ

DQa, DQb, DQa,DQb

DQc, DQd DQc,DQd

BWbBWb

BWEBWE

CLK

BWaBWa

GW GW

BYTE b

WRITE

DQ

BYTE a

WRITE

DQ

CE1 CE

CE2 CE2

CE3CE2

ZZ ZZ

OE OE

ADASDPSP

AA

ADASDCSC

Power Down Logic

ENABLE

DQ

DQ

Input

Register

17

Address

Register

OUTPUT

REGISTER

CLR

DQ

DQa, DQb, DQa,DQb

ADAVDV

A0-AA11-A0

MOMDOEDE

Binary

Counter

& Logic

Notes:

1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.

2. CE3 is for TA version only.

Document #: 38-05258 Rev. *A

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