CY7C1338B 데이터 시트보기 (PDF) - Cypress Semiconductor
부품명
상세내역
일치하는 목록
CY7C1338B Datasheet PDF : 18 Pages
| |||
CY7C1338B
Pin Configurations (continued)
119-Ball BGA
CY7C1338B (128K x 32)
1
2
3
4
5
6
7
A
VDDQ
A
B
NC
CE2
C
NC
A
D
DQc
NC
E
DQc
DQc
F
VDDQ
DQc
G
DQc
DQc
H
DQc
DQc
J
VDDQ
VDD
K
DQd
DQd
A
A
A
VSS
VSS
VSS
BWc
VSS
NC
VSS
ADSP
ADSC
VDD
NC
CE1
OE
ADV
GW
VDD
CLK
A
A
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
A
NC
A
NC
DQb
DQb
DQb
DQb
VDD
DQa
VDDQ
NC
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
L
DQd
DQd
M
VDDQ
DQd
N
DQd
DQd
BWd
VSS
VSS
NC
BWE
A1
BWa
VSS
VSS
DQa
DQa
DQa
DQa
VDDQ
DQa
P
DQd
NC
VSS
A0
VSS
NC
DQa
R
NC
A
MODE VDD
VDD
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Pin Descriptions
Name
ADSC
I/O
Input-
Synchronous
ADSP Input-
Synchronous
A[1:0]
A[16:2]
Input-
Synchronous
Input-
Synchronous
BW[3:0] Input-
Synchronous
ADV
BWE
GW
CLK
CE1
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[16:0] is
captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[16:0] is
captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
A1, A0 Address Inputs. These inputs feed the on-chip burst counter as the LSBs as well as being
used to access a particular memory location in the memory array.
Address Inputs used in conjunction with A[1:0] to select one of the 64K address locations. Sampled
at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled active, and ADSP or ADSC is active
LOW.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the
rising edge. BW0 controls DQ[7:0] and DP0, BW1 controls DQ[15:8] and DP1, BW2 controls DQ[23:16]
and DP2, and BW3 controls DQ[31:24] and DP3. See Write Cycle Descriptions table for further details.
Advance Input used to advance the on-chip address counter. When LOW the internal burst counter
is advanced in a burst sequence. The burst sequence is selected using the MODE input.
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct
a global write, independent of the state of BWE and BW[3:0]. Global writes override byte writes.
Clock Input. Used to capture all synchronous inputs to the device.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select/deselect the device. CE1 gates ADSP.
Document #: 38-05143 Rev. **
Page 3 of 18
Share Link: 