CY7C1009BN 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1009BN

128K x 8 Static RAM

Cypress Semiconductor 

CY7C109BN

CY7C1009BN

Data Retention Characteristics Over the Operating Range (Low Power version only)

Parameter

Description

VDR

ICCDR

tCDR

tR

VCC for Data Retention

Data Retention Current

Chip Deselect to Data Retention Time

Operation Recovery Time

Conditions

No input may exceed VCC + 0.5V

VCC = VDR = 2.0V,

CE1 > VCC – 0.3V or CE2 < 0.3V,

VIN > VCC – 0.3V or VIN < 0.3V

Data Retention Waveform

Min. Max Unit

2.0

V

150 µA

0

ns

200

µs

DATA RETENTION MODE

VCC

4.5V

VDR > 2V

4.5V

tCDR

tR

CE

Switching Waveforms

Read Cycle No. 1[10, 11]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No. 2 (OE Controlled)[11, 12]

DATA VALID

ADDRESS

CE1

CE2

OE

DATA OUT

VCC

SUPPLY

CURRENT

tRC

tACE

tDOE

tLZOE

HIGH IMPEDANCE

tLZCE

tPU

50%

Notes:

10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.

11. WE is HIGH for read cycle.

12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.

DATA VALID

tHZOE

tHZCE

HIGH

IMPEDANCE

tPD

ICC

50%

ISB

Document #: 001-06430 Rev. **

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