CY7C026A-15AXI 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C026A-15AXI Datasheet PDF : 21 Pages
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CY7C026A16K x 16 Dual-Port Static RAM
CY7C026A
16K x 16 Dual-Port Static RAM
Features
■ True dual-ported memory cells that allow simultaneous access
of the same memory location
■ 16K x 16 organization (CY7C026A)
■ 0.35 micron CMOS for optimum speed and power
■ High speed access: 15, and 20 ns
■ Low operating power
■ Active: ICC = 180 mA (typical)
■ Standby: ISB3 = 0.05 mA (typical)
■ Fully asynchronous operation
■ Automatic power-down
Logic Block Diagram
R/WL
UBL
■ Expandable data bus to 32 bits or more using Master/Slave
chip select when using more than one device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flags for port-to-port communication
■ Separate upper-byte and lower-byte control
■ Pin select for Master or Slave
■ Commercial and Industrial temperature ranges
■ Available in 100-pin thin quad plastic flatpack (TQFP)
■ Pb-free packages available
R/WR
UBR
CEL
LBL
OEL
8
I/O8L–I/O15[1L]
I/O0L–I/O[72L]
8
I/O
Control
I/O
Control
CER
LBR
OER
8
I/O8L–I/[O1]15R
8
I/O0L–I/O[2]7R
A0L–A13L
14
Address
Decode
True Dual-Ported
RAM Array
14
A0L–A13L
CEL
OEL
R/WL
SEML
BUSYL [3]
INTL
UBL
LBL
Notes
1. I/O8–I/O15 for x16 devices.
2. I/O0–I/O7 for x16 devices.
3. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
M/S
Address
14
Decode
14
A0R–A13R
A0R–A13R
CER
OER
R/WR
SEMR
[3] BUSYR
INTR
UBR
LBR
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-06046 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 14, 2011
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