CY7C006A-20JXC(2013) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C006A-20JXC
(Rev.:2013)

16 K × 8 Dual-Port Static RAM

Cypress Semiconductor 

CY7C006A

Switching Waveforms

Figure 4. Read Cycle No. 1 (Either Port Address Access) [16, 17, 18]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

DATA VALID

tOHA

Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) [16, 19, 20]

CE

OE

DATA OUT

ICC

CURRENT ISB

tACE

tDOE

tLZOE

tLZCE

tPU

tHZCE

tHZOE

DATA VALID

tPD

Figure 6. Read Cycle No. 3 (Either Port) [16, 18, 19, 20]

ADDRESS

tRC

tAA

tOHA

CE

DATA OUT

tLZCE

tABE

tACE

tLZCE

tHZCE

Notes

16. R/W is HIGH for read cycles.

17. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.

18. OE = VIL.

19. Address valid prior to or coincident with CE transition LOW.

20. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

Document Number: 38-06045 Rev. *G

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