CY7B9911(2007) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7B9911
(Rev.:2007)

Programmable Skew Clock Buffer

Cypress Semiconductor 

CY7B9911

RoboClock+™

Programmable Skew Clock Buffer

Features

■ All output pair skew <100 ps typical (250 max)

■ 3.75 to 100 MHz output operation

■ User selectable output functions

❐ Selectable skew to 18 ns

❐ Inverted and non-inverted

❐ Operation at ½ and ¼ input frequency

❐ Operation at 2x and 4x input frequency (input as low as 3.75

MHz)

■ Zero input to output delay

■ 50% duty cycle outputs

■ Outputs drive 50Ω terminated lines

■ Low operating current

■ 32-pin PLCC/LCC package

■ Jitter < 200 ps peak-to-peak (< 25 ps RMS)

Logic Block Diagram

TEST

Functional Description

The CY7B9911 High Speed Programmable Skew Clock Buffer

(PSCB) offers user selectable control over system clock

functions. This multiple output clock driver provides the system

integrator with functions necessary to optimize the timing of high

performance computer systems. Each of the eight individual TTL

drivers, arranged in four pairs of user controllable outputs, can

drive terminated transmission lines with impedances as low as

50Ω. They deliver minimal and specified output skews and full

swing logic levels.

Each output is hardwired to one of nine delay or function config-

urations. Delay increments of 0.6 to 1.5 ns are determined by the

operating frequency with outputs able to skew up to ±6 time units

from their nominal “zero” skew position. The completely

integrated PLL allows cancellation of external load and trans-

mission line delay effects. When this “zero delay” capability of the

PSCB is combined with the selectable output skew functions,

you can create output-to-output delays of up to ±12 time units.

Divide-by-two and divide-by-four output functions are provided

for additional flexibility in designing complex clock systems.

When combined with the internal PLL, these divide functions

enable distribution of a low frequency clock that is multiplied by

two or four at the clock destination. This facility minimizes clock

distribution difficulty enabling maximum system clock speed and

flexibility.

FB

REF

PHASE

FREQ FILTER

DET

VCO AND

TIME UNIT

GENERATOR

FS

4F0

4Q0

4F1

SELECT

4Q1

INPUTS

(THREE

LEVEL)

3F0

SKEW

3Q0

3F1

3Q1

SELECT

2Q0

2F0

2F1

MATRIX

2Q1

1F0

1Q0

1F1

1Q1

Cypress Semiconductor Corporation • 198 Champion Court

Document Number: 38-07209 Rev. *B

• San Jose, CA 95134-1709 • 408-943-2600

Revised June 20, 2007

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