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CY2309NZ(2004) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY2309NZ
(Rev.:2004)
Cypress
Cypress Semiconductor Cypress
CY2309NZ Datasheet PDF : 5 Pages
1 2 3 4 5
CY2309NZ
Maximum Ratings
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Input Voltage (Except REF) ............–0.5V to VDD + 0.5V
DC Input Voltage REF......................................... –0.5V to 7V
Storage Temperature ................................. –65°C to +150°C
Junction Temperature ................................................. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................ >2,000V
Operating Conditions for Commercial and Industrial Temperature Devices
Parameter
VDD
TA
CL
CIN
BUF_IN, SDRAM [1:9]
tPU
Description
Supply Voltage
(Ambient Operating Temperature) Commercial
(Ambient Operating Temperature) Industrial
Load Capacitance, Fout < 100 MHz
Load Capacitance,100 MHz < Fout < 133.33 MHz
Input Capacitance
Operating Frequency
Power-up time for all VDDs to reach minimum specified
voltage (power ramps must be monotonic)
Min.
3.0
0
–40
DC
0.05
Max.
3.6
70
85
30
15
7
133.33
50
Unit
V
°C
°C
pF
pF
pF
MHz
ms
Electrical Characteristics for Commercial and Industrial Temperature Devices
Parameter
VIL
VIH
IIL
IIH
VOL
VOH
IDD
Description
Input LOW Voltage[1]
Input HIGH Voltage[1]
Input LOW Current
Input HIGH Current
Output LOW Voltage[2]
Output HIGH Voltage[2]
Supply Current
Test Conditions
VIN = 0V
VIN = VDD
IOL = 8 mA
IOH = –8 mA
Unloaded outputs at 66.66 MHz
Switching Characteristics for Commercial and Industrial Temperature Devices[3]
Parameter
t3
t4
t5
t6
Name
Duty Cycle[2] = t2 ÷ t1
Rise Time[2]
Fall Time[2]
Output to Output Skew[2]
Description
Measured at 1.4V
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
Propagation Delay, BUF_IN Measured at VDD/2
Rising Edge to OUTPUT
Rising Edge[2]
Min.
40.0
1
Min.
2.0
2.4
Typ.
50.0
5
Max.
0.8
50.0
100.0
0.4
32
Max.
60.0
1.50
1.50
250
9.2
Unit
V
V
µA
µA
V
V
mA
Unit
%
ns
ns
ps
ns
Switching Waveforms
Duty Cycle Timing
1.4V
t1
t2
1.4V
1.4V
Notes:
1. BUF_IN input has a threshold voltage of VDD/2.
2. Parameter is guaranteed by design and characterization. It is not 100% tested in production.
3. All parameters specified with loaded outputs.
Document #: 38-07182 Rev. *C
Page 2 of 5

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