CY22394ZC-XXX 데이터 시트보기 (PDF) - Cypress Semiconductor
부품명
상세내역
일치하는 목록
CY22394ZC-XXX Datasheet PDF : 17 Pages
| |||
CY22393
CY22394
CY22395
Digital VCXO
The serial programming interface is used to dynamically
change the capacitor load value on the crystal. A change in
crystal load capacitance corresponds with a change in the
reference frequency.
For special pullable crystals specified by Cypress, the capac-
itance pull range is +150 ppm to –150 ppm from midrange.
Be aware that adjusting the frequency of the reference affects
all frequencies on all PLLs in a similar manner since all
frequencies are derived from the single reference.
Output Configuration
Under normal operation there are four internal frequency
sources that are routed via a programmable cross point switch
to any of the four programmable 7-bit output dividers. The four
sources are: reference, PLL1, PLL2, and PLL3. The following
is a description of each output.
CLKA’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of the two programmable
registers. See the section on “General Purpose Inputs” on
page 4 for more information.
CLKB’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of the two programmable
registers. See the section on “General Purpose Inputs” on
page 4 for more information.
CLKC’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
CLKD’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register. For
the CY22394, CLKD is brought out as the complimentary
version of a LV PECL Clock referenced to CLKE, bypassing
both the cross point switch and 7-bit post divider.
CLKE’s output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4. For the
CY22394, CLKE is brought out as a low voltage PECL Clock,
bypassing the post divider.
XBUF is the buffered reference.
The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15 pF. While
driving multiple loads is possible with the proper termination it
is generally not recommended.
Power-Saving Features
The SHUTDOWN/OE input tri-states the outputs when pulled
LOW. If system shutdown is enabled, a LOW on this pin also
shuts off the PLLs, counters, reference oscillator, and all other
active components. The resulting current on the VDD pins is
less than 5 mA (typical). Relock the PLLs after leaving
shutdown mode.
The S2/SUSPEND input is configured to shut down a custom-
izable set of outputs and/or PLLs, when LOW. All PLLs and
any of the outputs are shut off in nearly any combination. The
only limitation is that if a PLL is shut off, all outputs derived from
it must also be shut off. Suspending a PLL shuts off all
associated logic, while suspending an output simply forces a
tri-state condition.
With the serial interface, each PLL and/or output is individually
disabled. This provides total control over the power savings.
Improving Jitter
Jitter Optimization Control is useful for mitigating problems
related to similar clocks switching at the same moment,
causing excess jitter. If one PLL is driving more than one
output, the negative phase of the PLL can be selected for one
of the outputs (CLKA–CLKD). This prevents the output edges
from aligning, allowing superior jitter performance.
Power Supply Sequencing
For parts with multiple VDD pins, there are no power supply
sequencing requirements. The part is not fully operational until
all VDD pins have been brought up to the voltages specified in
the Operating Conditions[2] Table on page 12.
All grounds should be connected to the same ground plane.
CyClocksRT Software
CyClocksRT is our second generation software application
that allows users to configure this family of devices. The
easy-to-use interface offers complete control of the many
features of this family including, but not limited to, input
frequency, PLL and output frequencies, and different
functional options. It checks data sheet frequency range limita-
tions and automatically applies performance tuning.
CyClocksRT also has a power estimation feature that allows
the user to see the power consumption of a specific configu-
ration. You can download a free copy of CyberClocks that
includes CyClocksRT for free on Cypress’s web site at
www.cypress.com.
CyClocksRT is used to generate P, Q, and divider values used
in serial programming. There are many internal frequency
rules that are not documented in this data sheet, but are
required for proper operation of the device. Check these rules
by using the latest version of CyClocksRT.
Junction Temperature Limitations
It is possible to program this family such that the maximum
Junction Temperature rating is exceeded. The package θJA is
115 °C/W. Use the CyClocksRT power estimation feature to
verify that the programmed configuration meets the Junction
Temperature and Package Power Dissipation maximum
ratings.
Dynamic Updates
The output divider registers are not synchronized with the
output clocks. Changing the divider value of an active output
will likely cause a glitch on that output.
PLL P and Q data is spread between three bytes. Each byte
becomes active on the acknowledge for that byte, so changing
P and Q data for an active PLL will likely cause the PLL to try
to lock on an out-of-bounds condition. For this reason, turn off
the PLL being programmed during the update. Do this by
setting the PLL*_En bit LOW.
PLL1, CLKA, and CLKB each have multiple registers
supplying data. To program these resources safely, always
Document #: 38-07186 Rev. *C
Page 5 of 17
[+] Feedback
Share Link: 