CY22394FXIT 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY22394FXIT Datasheet PDF : 17 Pages
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Serial Programming Interface Timing
Figure 4. Start and Stop Frame
START
Transition
to next Bit
STOP
CY22393
CY22394
CY22395
SDAT
SCLK
Figure 5. Frame Format (Device Address, R/W, Register Address, Register Data)
SDAT
+
+
+
START DA6 DA5 DA0 R/W ACK
RA7 RA6 RA1 RA0 ACK D7 D6 D1 D0
ACK
SCLK
+
+
+
STOP
Serial Programming Interface Timing Specifications
Parameter
Description
Min
Max
Unit
fSCLK
Frequency of SCLK
–
Start mode time from SDA LOW to SCL LOW
0.6
400
kHz
–
μs
CLKLOW
CLKHIGH
tSU
tDH
SCLK LOW period
SCLK HIGH period
Data transition to SCLK HIGH
Data hold (SCLK LOW to data transition)
Rise time of SCLK and SDAT
1.3
–
μs
0.6
–
μs
100
–
ns
0
–
ns
–
300
ns
Fall time of SCLK and SDAT
–
300
ns
Stop mode time from SCLK HIGH to SDAT HIGH
0.6
–
μs
Stop mode to Start mode
1.3
–
μs
Absolute Maximum Conditions
Supply Voltage ............................................... –0.5V to +7.0V
DC Input Voltage............................ –0.5V to + (AVDD + 0.5V)
Storage Temperature .................................. –65°C to +125°C
Junction Temperature .................................................. 125°C
Data Retention @ Tj=125×C................................. > 10 years
Maximum Programming Cycles ....................................... 100
Package Power Dissipation ......................................350 mW
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ........................... > 2000V
Latch up (per JEDEC 17) .................................... > ±200 mA
Stresses exceeding Absolute Maximum Conditions may
cause permanent damage to the device. These conditions are
stress ratings only. Functional operation of the device at these
or any other conditions beyond those indicated in the
operation sections of this data sheet is not implied. Extended
exposure to Absolute Maximum Conditions may affect
reliability.
Document #: 38-07186 Rev. *C
Page 11 of 17
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