CY22394ZXI-XXXT(2008) 데이터 시트보기 (PDF) - Cypress Semiconductor

부품명

상세내역

일치하는 목록

CY22394ZXI-XXXT
(Rev.:2008)

Three-PLL Serial-Programmable Flash-Programmable Clock Generator

Cypress Semiconductor 

CY22393, CY22394, CY22395

Operation

The CY22393, CY22394, and CY22395 are a family of parts

designed as upgrades to the existing CY22392 device. These

parts have similar performance to the CY22392, but provide

advanced features to meet the needs of more demanding

applications.

The clock family has three PLLs which, when combined with the

reference, allow up to four independent frequencies to be output

on up to six pins. These three PLLs are completely

programmable.

Configurable PLLs

PLL1 generates a frequency that is equal to the reference

divided by an 8-bit divider (Q) and multiplied by an 11-bit divider

in the PLL feedback loop (P). The output of PLL1 is sent to two

locations: the cross point switch and the PECL output

(CY22394). The output of PLL1 is also sent to a /2, /3, or /4

synchronous post-divider that is output through CLKE. The

frequency of PLL1 can be changed using serial programming or

by external CMOS inputs, S0, S1, and S2. See the following

section on General Purpose Inputs for more detail.

PLL2 generates a frequency that is equal to the reference

divided by an 8-bit divider (Q) and multiplied by an 11-bit divider

in the PLL feedback loop (P). The output of PLL2 is sent to the

cross point switch. The frequency of PLL2 is changed using

serial programming.

PLL3 generates a frequency that is equal to the reference

divided by an 8-bit divider (Q) and multiplied by an 11-bit divider

in the PLL feedback loop (P). The output of PLL3 is sent to the

cross point switch. The frequency of PLL3 is changed using

serial programming.

General Purpose Inputs

S2 is a general purpose input that is programmed to allow for two

different frequency settings. Options that switches with this

general purpose input are as follows: the frequency of PLL1, the

output divider of CLKB, and the output divider of CLKA.

The two frequency settings are contained within an eight-row

frequency table. The values of SCLK (S1) and SDAT (S0) pins

are latched during start up and used as the other two indexes

into this array.

CLKA and CLKB have seven-bit dividers that point to one of the

two programmable settings (register 0 and register 1). Both

clocks share a single register control and both must be set to

register 0, or both must be set to register 1.

For example, the part may be programmed to use S0, S1, and

S2 (0,0,0 to 1,1,1) to control eight different values of P and Q on

PLL1. For each PLL1 P and Q setting, one of the two CLKA and

CLKB divider registers can be chosen. Any divider change as a

result of switching S0, S1, or S2 is guaranteed to be glitch free.

Crystal Input

The input crystal oscillator is an important feature of this family

of parts because of its flexibility and performance features.

The oscillator inverter has programmable drive strength. This

allows for maximum compatibility with crystals from various

manufacturers, process, performance, and quality.

The input load capacitors are placed on-die to reduce external

component cost. These capacitors are true parallel-plate

capacitors for ultra-linear performance. These were chosen to

reduce the frequency shift that occurs when nonlinear load

capacitance interacts with load, bias, supply, and temperature

changes. Nonlinear (FET gate) crystal load capacitors must not

be used for MPEG, POTS dial tone, communications, or other

applications that are sensitive to absolute frequency

requirements.

The value of the load capacitors is determined by six bits in a

programmable register. The load capacitance can be set with a

resolution of 0.375pF for a total crystal load range of 6pF to 30pF.

For driven clock inputs, the input load capacitors can be

completely bypassed. This allows the clock chip to accept driven

frequency inputs up to 166 MHz. If the application requires a

driven input, leave XTALOUT floating.

Digital VCXO

The serial programming interface is used to dynamically change

the capacitor load value on the crystal. A change in crystal load

capacitance corresponds with a change in the reference

frequency.

For special pullable crystals specified by Cypress, the

capacitance pull range is +150 ppm to –150 ppm from midrange.

Be aware that adjusting the frequency of the reference affects all

frequencies on all PLLs in a similar manner since all frequencies

are derived from the single reference.

Output Configuration

Under normal operation there are four internal frequency

sources that are routed through a programmable cross point

switch to any of the four programmable 7-bit output dividers. The

four sources are: reference, PLL1, PLL2, and PLL3. The

following is a description of each output.

CLKA’s output originates from the cross point switch and goes

through a programmable 7-bit post divider. The 7-bit post divider

derives its value from one of the two programmable registers.

See the section on “General Purpose Inputs” on page 5 for more

information.

CLKB’s output originates from the cross point switch and goes

through a programmable 7-bit post divider. The 7-bit post divider

derives its value from one of the two programmable registers.

See the section on “General Purpose Inputs” on page 5 for more

information.

CLKC’s output originates from the cross point switch and goes

through a programmable 7-bit post divider. The 7-bit post divider

derives its value from one programmable register.

CLKD’s output originates from the cross point switch and goes

through a programmable 7-bit post divider. The 7-bit post divider

derives its value from one programmable register. For the

CY22394, CLKD is brought out as the complimentary version of

a LV PECL Clock referenced to CLKE, bypassing both the cross

point switch and 7-bit post divider.

CLKE’s output originates from PLL1 and goes through a post

divider that may be programmed to /2, /3, or /4. For the CY22394,

CLKE is brought out as a low voltage PECL Clock, bypassing the

post divider.

XBUF is the buffered reference.

Document #: 38-07186 Rev. *D

Page 5 of 19

[+] Feedback

Share Link: